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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
9d113548
编写于
6月 02, 2022
作者:
L
Lingrui98
浏览文件
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电子邮件补丁
差异文件
tage, ittage: add perf counter to count outstanding update requests
上级
fc51b1f6
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
40 addition
and
1 deletion
+40
-1
src/main/scala/xiangshan/frontend/ITTAGE.scala
src/main/scala/xiangshan/frontend/ITTAGE.scala
+21
-1
src/main/scala/xiangshan/frontend/Tage.scala
src/main/scala/xiangshan/frontend/Tage.scala
+19
-0
未找到文件。
src/main/scala/xiangshan/frontend/ITTAGE.scala
浏览文件 @
9d113548
...
...
@@ -258,7 +258,7 @@ class ITTageTable
)
}
val
bank_conflict
=
(
0
until
nBanks
).
map
(
b
=>
table_banks
(
b
).
io
.
w
.
req
.
valid
&&
s0_bank_req_1h
(
b
)).
reduce
(
_
||
_
)
val
bank_conflict
=
(
0
until
nBanks
).
map
(
b
=>
table_banks
(
b
).
io
.
w
.
req
.
valid
&&
s0_bank_req_1h
(
b
)
&&
io
.
req
.
valid
).
reduce
(
_
||
_
)
io
.
req
.
ready
:=
!
io
.
update
.
valid
// io.req.ready := !bank_conflict
XSPerfAccumulate
(
f
"ittage_table_bank_conflict"
,
bank_conflict
)
...
...
@@ -292,6 +292,26 @@ class ITTageTable
XSPerfAccumulate
(
"ittage_table_updates"
,
io
.
update
.
valid
)
XSPerfAccumulate
(
"ittage_table_hits"
,
io
.
resp
.
valid
)
val
fakeWriteBufferWidth
=
3
val
fakePerBankWriteBuffer
=
Seq
.
fill
(
nBanks
)(
RegInit
(
0.
U
(
fakeWriteBufferWidth
.
W
)))
for
(
b
<-
0
until
nBanks
)
{
val
oldValue
=
fakePerBankWriteBuffer
(
b
)
val
thisBankHasUpdate
=
io
.
update
.
valid
&&
update_req_bank_1h
(
b
)
val
thisBankHasRead
=
io
.
req
.
valid
&&
s0_bank_req_1h
(
b
)
when
(
thisBankHasUpdate
&&
thisBankHasRead
)
{
fakePerBankWriteBuffer
(
b
)
:=
satUpdate
(
oldValue
,
fakeWriteBufferWidth
,
true
.
B
)
}
.
elsewhen
(!
thisBankHasUpdate
&&
!
thisBankHasRead
)
{
fakePerBankWriteBuffer
(
b
)
:=
satUpdate
(
oldValue
,
fakeWriteBufferWidth
,
false
.
B
)
}
for
(
i
<-
0
until
(
1
<<
fakeWriteBufferWidth
))
{
XSPerfAccumulate
(
f
"ittage_table_${tableIdx}_bank_${b}_write_buffer_has_req_${i}"
,
fakePerBankWriteBuffer
(
b
)
===
i
.
U
)
}
XSPerfAccumulate
(
f
"ittage_table_${tableIdx}_bank_${b}_write_buffer_overflow"
,
fakePerBankWriteBuffer
(
b
).
andR
()
&&
thisBankHasUpdate
&&
thisBankHasRead
)
}
if
(
BPUDebug
&&
debug
)
{
val
u
=
io
.
update
val
idx
=
s0_idx
...
...
src/main/scala/xiangshan/frontend/Tage.scala
浏览文件 @
9d113548
...
...
@@ -484,6 +484,25 @@ class TageTable
}
}
val
fakeWriteBufferWidth
=
4
val
fakePerBankWriteBuffer
=
Seq
.
fill
(
nBanks
)(
RegInit
(
0.
U
(
fakeWriteBufferWidth
.
W
)))
for
(
b
<-
0
until
nBanks
)
{
val
oldValue
=
fakePerBankWriteBuffer
(
b
)
val
thisBankHasUpdate
=
io
.
update
.
mask
.
reduce
(
_
||
_
)
&&
update_req_bank_1h
(
b
)
&&
per_bank_not_silent_update
(
b
).
reduce
(
_
||
_
)
val
thisBankHasRead
=
io
.
req
.
valid
&&
s0_bank_req_1h
(
b
)
when
(
thisBankHasUpdate
&&
thisBankHasRead
)
{
fakePerBankWriteBuffer
(
b
)
:=
satUpdate
(
oldValue
,
fakeWriteBufferWidth
,
true
.
B
)
}
.
elsewhen
(!
thisBankHasUpdate
&&
!
thisBankHasRead
)
{
fakePerBankWriteBuffer
(
b
)
:=
satUpdate
(
oldValue
,
fakeWriteBufferWidth
,
false
.
B
)
}
for
(
i
<-
0
until
(
1
<<
fakeWriteBufferWidth
))
{
XSPerfAccumulate
(
f
"tage_table_${tableIdx}_bank_${b}_write_buffer_has_req_${i}"
,
fakePerBankWriteBuffer
(
b
)
===
i
.
U
)
}
XSPerfAccumulate
(
f
"tage_table_${tableIdx}_bank_${b}_write_buffer_overflow"
,
fakePerBankWriteBuffer
(
b
).
andR
()
&&
thisBankHasUpdate
&&
thisBankHasRead
)
}
val
u
=
io
.
update
val
b
=
PriorityEncoder
(
u
.
mask
)
val
ub
=
PriorityEncoder
(
u
.
uMask
)
...
...
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