LoadUnit, Lsroq: dump forwardData and forwardMask.

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -189,13 +189,22 @@ class LoadUnit extends XSModule {
 
   PipelineConnect(l4_out, l5_in, io.ldout.fire() || l5_in.bits.miss && l5_in.valid, false.B)
 
-  XSDebug(l4_valid, "l4: pc 0x%x addr 0x%x -> 0x%x op %b data 0x%x mask %x dcache %b mmio %b\n",
+  XSDebug(l4_valid, "l4: pc 0x%x addr 0x%x -> 0x%x op %b data 0x%x mask %x forwardData: 0x%x forwardMask: %x dcache %b mmio %b\n",
     l4_out.bits.uop.cf.pc, l4_out.bits.vaddr, l4_out.bits.paddr,
     l4_out.bits.uop.ctrl.fuOpType, l4_out.bits.data, l4_out.bits.mask,
-    l4_dcache, l4_mmio)
+    l4_out.bits.forwardData.asUInt, l4_out.bits.forwardMask.asUInt, l4_dcache, l4_mmio)
+
+  XSDebug(l5_in.valid, "L5: pc 0x%x addr 0x%x -> 0x%x op %b data 0x%x mask %x forwardData: 0x%x forwardMask: %x\n",
+    l5_in.bits.uop.cf.pc,  l5_in.bits.vaddr, l5_in.bits.paddr,
+    l5_in.bits.uop.ctrl.fuOpType , l5_in.bits.data,  l5_in.bits.mask,
+    l5_in.bits.forwardData.asUInt, l5_in.bits.forwardMask.asUInt)
+
+  XSDebug(l4_valid, "l4: sbuffer forwardData: 0x%x forwardMask: %x\n",
+    io.sbuffer.forwardData.asUInt, io.sbuffer.forwardMask.asUInt)
+
+  XSDebug(l4_valid, "l4: lsroq forwardData: 0x%x forwardMask: %x\n",
+    io.lsroq.forward.forwardData.asUInt, io.lsroq.forward.forwardMask.asUInt)
 
-  XSDebug(l5_in.valid, "L5: pc 0x%x addr 0x%x -> 0x%x op %b data 0x%x mask %x\n",
-    l5_in.bits.uop.cf.pc,  l5_in.bits.vaddr , l5_in.bits.paddr , l5_in.bits.uop.ctrl.fuOpType , l5_in.bits.data,  l5_in.bits.mask )
 
   //-------------------------------------------------------
   // LD Pipeline Stage 5

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -105,22 +105,28 @@ class Lsroq extends XSModule {
   (0 until LoadPipelineWidth).map(i => {
     when(io.loadIn(i).fire()) {
       when(io.loadIn(i).bits.miss) {
-        XSInfo(io.loadIn(i).valid, "load miss write to lsroq idx %d pc 0x%x vaddr %x paddr %x data %x mmio %x roll %x\n",
+        XSInfo(io.loadIn(i).valid, "load miss write to lsroq idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x\n",
           io.loadIn(i).bits.uop.lsroqIdx,
           io.loadIn(i).bits.uop.cf.pc,
           io.loadIn(i).bits.vaddr,
           io.loadIn(i).bits.paddr,
           io.loadIn(i).bits.data,
+          io.loadIn(i).bits.mask,
+          io.loadIn(i).bits.forwardData.asUInt,
+          io.loadIn(i).bits.forwardMask.asUInt,
           io.loadIn(i).bits.mmio,
           io.loadIn(i).bits.rollback
         )
       }.otherwise {
-        XSInfo(io.loadIn(i).valid, "load hit write to cbd idx %d pc 0x%x vaddr %x paddr %x data %x mmio %x roll %x\n",
+        XSInfo(io.loadIn(i).valid, "load hit write to cbd idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x\n",
           io.loadIn(i).bits.uop.lsroqIdx,
           io.loadIn(i).bits.uop.cf.pc,
           io.loadIn(i).bits.vaddr,
           io.loadIn(i).bits.paddr,
           io.loadIn(i).bits.data,
+          io.loadIn(i).bits.mask,
+          io.loadIn(i).bits.forwardData.asUInt,
+          io.loadIn(i).bits.forwardMask.asUInt,
           io.loadIn(i).bits.mmio,
           io.loadIn(i).bits.rollback
         )