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体验新版 GitCode,发现更多精彩内容 >>
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984c6ad7
编写于
10月 12, 2020
作者:
A
Allen
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差异文件
MissQueue: keep watching probe write backed block before we do
writeback.
上级
38f832fc
变更
1
隐藏空白更改
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1 changed file
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2 addition
and
1 deletion
+2
-1
src/main/scala/xiangshan/cache/missQueue.scala
src/main/scala/xiangshan/cache/missQueue.scala
+2
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未找到文件。
src/main/scala/xiangshan/cache/missQueue.scala
浏览文件 @
984c6ad7
...
@@ -362,7 +362,8 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
...
@@ -362,7 +362,8 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
// during refill, probe may step in, it may release our blocks
// during refill, probe may step in, it may release our blocks
// if it releases the block we are trying to acquire, we don't care, since we will get it back eventually
// if it releases the block we are trying to acquire, we don't care, since we will get it back eventually
// but we need to know whether it releases the block we are trying to evict
// but we need to know whether it releases the block we are trying to evict
val
prober_writeback_our_block
=
(
state
===
s_refill_req
||
state
===
s_refill_resp
)
&&
val
prober_writeback_our_block
=
(
state
===
s_refill_req
||
state
===
s_refill_resp
||
state
===
s_mem_finish
||
state
===
s_send_resp
||
state
===
s_wb_req
)
&&
io
.
probe_wb_req
.
valid
&&
!
io
.
probe_wb_req
.
bits
.
voluntary
&&
io
.
probe_wb_req
.
valid
&&
!
io
.
probe_wb_req
.
bits
.
voluntary
&&
io
.
probe_wb_req
.
bits
.
tag
===
req_old_meta
.
tag
&&
io
.
probe_wb_req
.
bits
.
tag
===
req_old_meta
.
tag
&&
io
.
probe_wb_req
.
bits
.
idx
===
req_idx
&&
io
.
probe_wb_req
.
bits
.
idx
===
req_idx
&&
...
...
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