Merge pull request #140 from RISCVERS/bug-boringutils

Fix boringutils bug by adjust the instantiation order of the front and back ends

src/main/scala/xiangshan/Bundle.scala

@@ -128,7 +128,7 @@ class Redirect extends XSBundle {
   val target = UInt(VAddrBits.W)
   val brTarget = UInt(VAddrBits.W)
   val brTag = new BrqPtr
-  val _type = UInt(2.W)
+  val btbType = UInt(2.W)
   //val isCall = Bool()
   val taken = Bool()
   val hist = UInt(HistoryLength.W)

src/main/scala/xiangshan/XSCore.scala

@@ -128,8 +128,8 @@ class XSCore(implicit p: XSConfig) extends XSModule {
 
   val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
 
-  val front = Module(new Frontend)
   val backend = Module(new Backend)
+  val front = Module(new Frontend)
 
   front.io.backend <> backend.io.frontend
 

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -224,17 +224,26 @@ class Brq extends XSModule {
   XSInfo(debug_roq_redirect, "roq redirect, flush brq\n")
 
   XSInfo(debug_brq_redirect, p"brq redirect, target:${Hexadecimal(io.redirect.bits.target)}\n")
-  val mbpInstr = io.out.fire()
-  val mbpRight = io.out.fire() && !commitEntry.misPred
-  val mbpWrong = io.out.fire() && commitEntry.misPred
-  val mbpBRight = io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B
-  val mbpBWrong = io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B
-  val mbpJRight = io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J
-  val mbpJWrong = io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J
-  val mbpIRight = io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I
-  val mbpIWrong = io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I
-  val mbpRRight = io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R
-  val mbpRWrong = io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R
+
+  val fire = io.out.fire()
+  val predRight = fire && !commitEntry.misPred
+  val predWrong = fire && commitEntry.misPred
+  val isBType = commitEntry.exuOut.redirect.btbType===BTBtype.B
+  val isJType = commitEntry.exuOut.redirect.btbType===BTBtype.J
+  val isIType = commitEntry.exuOut.redirect.btbType===BTBtype.I
+  val isRType = commitEntry.exuOut.redirect.btbType===BTBtype.R
+  val mbpInstr = fire
+  val mbpRight = predRight
+  val mbpWrong = predWrong
+  val mbpBRight = predRight && isBType
+  val mbpBWrong = predWrong && isBType
+  val mbpJRight = predRight && isJType
+  val mbpJWrong = predWrong && isJType
+  val mbpIRight = predRight && isIType
+  val mbpIWrong = predWrong && isIType
+  val mbpRRight = predRight && isRType
+  val mbpRWrong = predWrong && isRType
+
   if(EnableBPU){
     BoringUtils.addSource(mbpInstr, "MbpInstr")
     BoringUtils.addSource(mbpRight, "MbpRight")

src/main/scala/xiangshan/backend/exu/AluExeUnit.scala

@@ -62,7 +62,7 @@ class AluExeUnit extends Exu(Exu.aluExeUnitCfg) {
   io.out.bits.redirect.target := Mux(!taken && isBranch, pcLatchSlot, target)
   io.out.bits.redirect.brTarget := target
   io.out.bits.redirect.brTag := uop.brTag
-  io.out.bits.redirect._type := "b00".U  
+  io.out.bits.redirect.btbType := "b00".U  
   io.out.bits.redirect.taken := isBranch && taken
   io.out.bits.redirect.hist := uop.cf.hist
   io.out.bits.redirect.tageMeta := uop.cf.tageMeta

src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala

@@ -43,7 +43,7 @@ class JmpExeUnit(implicit val p: XSConfig) extends Exu(Exu.jmpExeUnitCfg) {
   val uop = io.in.bits.uop
   csrExuOut.redirect.pc := uop.cf.pc
   csrExuOut.redirect.brTarget := DontCare // DontCare
-  csrExuOut.redirect._type := LookupTree(uop.ctrl.fuOpType, RV32I_BRUInstr.bruFuncTobtbTypeTable)
+  csrExuOut.redirect.btbType := LookupTree(uop.ctrl.fuOpType, RV32I_BRUInstr.bruFuncTobtbTypeTable)
   csrExuOut.redirect.taken := false.B
   csrExuOut.redirect.hist := uop.cf.hist
   csrExuOut.redirect.tageMeta := uop.cf.tageMeta

src/main/scala/xiangshan/backend/fu/Jump.scala

@@ -25,7 +25,7 @@ class Jump extends FunctionUnit(jmpCfg){
   io.out.bits.redirect.target := target
   io.out.bits.redirect.brTarget := target // DontCare
   io.out.bits.redirect.brTag := uop.brTag
-  io.out.bits.redirect._type := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
+  io.out.bits.redirect.btbType := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
   io.out.bits.redirect.taken := true.B
   io.out.bits.redirect.hist := uop.cf.hist
   io.out.bits.redirect.tageMeta := uop.cf.tageMeta

src/main/scala/xiangshan/frontend/BPU.scala

@@ -103,7 +103,7 @@ class BPUStage1 extends XSModule {
   btb.io.update.oldCtr := r.btbPredCtr
   btb.io.update.taken := r.taken
   btb.io.update.target := r.brTarget
-  btb.io.update._type := r._type
+  btb.io.update.btbType := r.btbType
   // TODO: add RVC logic
   btb.io.update.isRVC := DontCare
 
@@ -116,7 +116,7 @@ class BPUStage1 extends XSModule {
   val btbCtrs = VecInit(btb.io.out.dEntries.map(_.pred))
   val btbValids = btb.io.out.hits
   val btbTargets = VecInit(btb.io.out.dEntries.map(_.target))
-  val btbTypes = VecInit(btb.io.out.dEntries.map(_._type))
+  val btbTypes = VecInit(btb.io.out.dEntries.map(_.btbType))
 
 
   val jbtac = Module(new JBTAC)
@@ -129,7 +129,7 @@ class BPUStage1 extends XSModule {
   jbtac.io.update.fetchPC := updateFetchpc
   jbtac.io.update.fetchIdx := r.fetchIdx << 1
   jbtac.io.update.misPred := io.redirectInfo.misPred
-  jbtac.io.update._type := r._type
+  jbtac.io.update.btbType := r.btbType
   jbtac.io.update.target := r.target
   jbtac.io.update.hist := r.hist
 
@@ -155,8 +155,8 @@ class BPUStage1 extends XSModule {
   updateGhr := io.s1OutPred.bits.redirect || io.flush
   val brJumpIdx = Mux(!(btbHit && btbTaken), 0.U, UIntToOH(btbTakenIdx))
   val indirectIdx = Mux(!jbtacHit, 0.U, UIntToOH(jbtacHitIdx))
-  //val newTaken = Mux(io.redirectInfo.flush(), !(r._type === BTBtype.B && !r.taken), )
-  newGhr := Mux(io.redirectInfo.flush(),    (r.hist << 1.U) | !(r._type === BTBtype.B && !r.taken),
+  //val newTaken = Mux(io.redirectInfo.flush(), !(r.btbType === BTBtype.B && !r.taken), )
+  newGhr := Mux(io.redirectInfo.flush(),    (r.hist << 1.U) | !(r.btbType === BTBtype.B && !r.taken),
             Mux(io.flush,                   Mux(io.s3Taken, (io.s3RollBackHist << 1.U) | 1.U, io.s3RollBackHist),
             Mux(io.s1OutPred.bits.redirect, (PriorityMux(brJumpIdx | indirectIdx, io.s1OutPred.bits.hist) << 1.U | 1.U),
                                             io.s1OutPred.bits.hist(0) << PopCount(btbNotTakens))))
@@ -192,8 +192,8 @@ class BPUStage1 extends XSModule {
   XSDebug(true.B, "[BPUS1]outPred:(%d) pc=0x%x, redirect=%d instrValid=%b tgt=%x\n",
     io.s1OutPred.valid, pcLatch, io.s1OutPred.bits.redirect, io.s1OutPred.bits.instrValid.asUInt, io.s1OutPred.bits.target)
   XSDebug(io.flush && io.redirectInfo.flush(),
-    "[BPUS1]flush from backend: pc=%x tgt=%x brTgt=%x _type=%b taken=%d oldHist=%b fetchIdx=%d isExcpt=%d\n",
-    r.pc, r.target, r.brTarget, r._type, r.taken, r.hist, r.fetchIdx, r.isException)
+    "[BPUS1]flush from backend: pc=%x tgt=%x brTgt=%x btbType=%b taken=%d oldHist=%b fetchIdx=%d isExcpt=%d\n",
+    r.pc, r.target, r.brTarget, r.btbType, r.taken, r.hist, r.fetchIdx, r.isException)
   XSDebug(io.flush && !io.redirectInfo.flush(),
     "[BPUS1]flush from Stage3:  s3Taken=%d s3RollBackHist=%b\n", io.s3Taken, io.s3RollBackHist)
 
@@ -300,7 +300,7 @@ class BPUStage3 extends XSModule {
   io.out.bits.predCtr := inLatch.btbPred.bits.predCtr
   io.out.bits.btbHitWay := inLatch.btbPred.bits.btbHitWay
   io.out.bits.tageMeta := inLatch.btbPred.bits.tageMeta
-  //io.out.bits._type := Mux(jmpIdx === retIdx, BTBtype.R,
+  //io.out.bits.btbType := Mux(jmpIdx === retIdx, BTBtype.R,
   //  Mux(jmpIdx === jalrIdx, BTBtype.I,
   //  Mux(jmpIdx === brTakenIdx, BTBtype.B, BTBtype.J)))
   val firstHist = inLatch.btbPred.bits.hist(0)

src/main/scala/xiangshan/frontend/Tage.scala

@@ -262,8 +262,8 @@ class Tage extends TageModule {
 
   val updateMeta = io.redirectInfo.redirect.tageMeta
   //val updateMisPred = UIntToOH(io.redirectInfo.redirect.fetchIdx) &
-  //  Fill(FetchWidth, (io.redirectInfo.misPred && io.redirectInfo.redirect._type === BTBtype.B).asUInt)
-  val updateMisPred = io.redirectInfo.misPred && io.redirectInfo.redirect._type === BTBtype.B
+  //  Fill(FetchWidth, (io.redirectInfo.misPred && io.redirectInfo.redirect.btbType === BTBtype.B).asUInt)
+  val updateMisPred = io.redirectInfo.misPred && io.redirectInfo.redirect.btbType === BTBtype.B
 
   val updateMask = WireInit(0.U.asTypeOf(Vec(TageNTables, Vec(BankWidth, Bool()))))
   val updateUMask = WireInit(0.U.asTypeOf(Vec(TageNTables, Vec(BankWidth, Bool()))))
@@ -317,8 +317,8 @@ class Tage extends TageModule {
     io.meta(w).allocate.bits := allocEntry
 
     val isUpdateTaken = io.redirectInfo.valid && io.redirectInfo.redirect.fetchIdx === w.U &&
-      io.redirectInfo.redirect.taken && io.redirectInfo.redirect._type === BTBtype.B
-    when (io.redirectInfo.redirect._type === BTBtype.B && io.redirectInfo.valid &&  io.redirectInfo.redirect.fetchIdx === w.U) {
+      io.redirectInfo.redirect.taken && io.redirectInfo.redirect.btbType === BTBtype.B
+    when (io.redirectInfo.redirect.btbType === BTBtype.B && io.redirectInfo.valid &&  io.redirectInfo.redirect.fetchIdx === w.U) {
       when (updateMeta.provider.valid) {
         val provider = updateMeta.provider.bits
 

src/main/scala/xiangshan/frontend/btb.scala

@@ -18,7 +18,7 @@ class BTBUpdateBundle extends XSBundle {
   val oldCtr = UInt(2.W)
   val taken = Bool()
   val target = UInt(VAddrBits.W)
-  val _type = UInt(2.W)
+  val btbType = UInt(2.W)
   val isRVC = Bool()
 }
 
@@ -37,7 +37,7 @@ class BTBPred extends XSBundle {
 case class btbDataEntry() extends XSBundle {
   val target = UInt(VAddrBits.W)
   val pred = UInt(2.W) // 2-bit saturated counter as a quick predictor
-  val _type = UInt(2.W)
+  val btbType = UInt(2.W)
   val isRVC = Bool()
 }
 
@@ -139,8 +139,8 @@ class BTB extends XSModule {
   // not taken branches from a valid entry
   val notTakenBranches = Wire(Vec(BtbBanks, Bool()))
   for (b <- 0 until BtbBanks) {
-    predTakens(b) := bankHits(b) && (dataRead(b)._type === BTBtype.J || dataRead(b)._type === BTBtype.B && dataRead(b).pred(1).asBool)
-    notTakenBranches(b) := bankHits(b) && dataRead(b)._type === BTBtype.B && !dataRead(b).pred(1).asBool
+    predTakens(b) := bankHits(b) && (dataRead(b).btbType === BTBtype.J || dataRead(b).btbType === BTBtype.B && dataRead(b).pred(1).asBool)
+    notTakenBranches(b) := bankHits(b) && dataRead(b).btbType === BTBtype.B && !dataRead(b).pred(1).asBool
   }
 
   // e.g: baseBank == 5 => (5, 6,..., 15, 0, 1, 2, 3, 4)
@@ -159,7 +159,7 @@ class BTB extends XSModule {
   // Priority mux which corresponds with inst orders
   // BTB only produce one single prediction
   val takenTarget = MuxCase(0.U, bankIdxInOrder.map(b => (predTakens(b), dataRead(b).target)))
-  val takenType   = MuxCase(0.U, bankIdxInOrder.map(b => (predTakens(b), dataRead(b)._type)))
+  val takenType   = MuxCase(0.U, bankIdxInOrder.map(b => (predTakens(b), dataRead(b).btbType)))
   // Record which inst is predicted taken
   val takenIdx = MuxCase(0.U, (0 until BtbBanks).map(b => (predTakens(bankIdxInOrder(b)), b.U)))
 
@@ -187,12 +187,12 @@ class BTB extends XSModule {
   val btbDataWrite = Wire(btbDataEntry())
   btbDataWrite.target := u.target
   btbDataWrite.pred := newCtr
-  btbDataWrite._type := u._type
+  btbDataWrite.btbType := u.btbType
   btbDataWrite.isRVC := u.isRVC
 
-  val isBr = u._type === BTBtype.B
-  val isJ = u._type === BTBtype.J
-  val notBrOrJ = u._type =/= BTBtype.B && u._type =/= BTBtype.J
+  val isBr = u.btbType === BTBtype.B
+  val isJ = u.btbType === BTBtype.J
+  val notBrOrJ = u.btbType =/= BTBtype.B && u.btbType =/= BTBtype.J
 
   // Do not update BTB on indirect or return, or correctly predicted J or saturated counters
   val noNeedToUpdate = (!u.misPred && (isBr && updateOnSaturated || isJ)) || (u.misPred && notBrOrJ)
@@ -218,18 +218,18 @@ class BTB extends XSModule {
   io.out.dEntries := VecInit((0 until BtbBanks by 2).map(b => dataRead(bankIdxInOrder(b))))
   io.out.hits := VecInit((0 until BtbBanks by 2).map(b => bankHits(bankIdxInOrder(b))))
 
-  XSDebug(io.in.pc.fire(), "[BTB]read: pc=0x%x, baseBank=%d, realMask=%b\n", io.in.pc.bits, baseBank, realMask)
-  XSDebug(nextFire, "[BTB]read_resp: pc=0x%x, readIdx=%d-------------------------------\n",
+  XSDebug(io.in.pc.fire(), "read: pc=0x%x, baseBank=%d, realMask=%b\n", io.in.pc.bits, baseBank, realMask)
+  XSDebug(nextFire, "read_resp: pc=0x%x, readIdx=%d-------------------------------\n",
     io.in.pcLatch, btbAddr.getIdx(io.in.pcLatch))
   for (i <- 0 until BtbBanks){
-    XSDebug(nextFire, "[BTB]read_resp[b=%d][r=%d]: valid=%d, tag=0x%x, target=0x%x, type=%d, ctr=%d\n",
-    i.U, realRowLatch(i), metaRead(i).valid, metaRead(i).tag, dataRead(i).target, dataRead(i)._type, dataRead(i).pred)
+    XSDebug(nextFire, "read_resp[b=%d][r=%d]: valid=%d, tag=0x%x, target=0x%x, type=%d, ctr=%d\n",
+    i.U, realRowLatch(i), metaRead(i).valid, metaRead(i).tag, dataRead(i).target, dataRead(i).btbType, dataRead(i).pred)
   }
-  XSDebug(nextFire, "[BTB]bankIdxInOrder:")
+  XSDebug(nextFire, "bankIdxInOrder:")
   for (i <- 0 until BtbBanks){ XSDebug(nextFire, "%d ", bankIdxInOrder(i))}
   XSDebug(nextFire, "\n")
-  XSDebug(io.redirectValid, "[BTB]update_req: pc=0x%x, hit=%d, misPred=%d, oldCtr=%d, taken=%d, target=0x%x, _type=%d\n",
-    u.pc, u.hit, u.misPred, u.oldCtr, u.taken, u.target, u._type)
-  XSDebug(io.redirectValid, "[BTB]update: noNeedToUpdate=%d, writeValid=%d, bank=%d, row=%d, newCtr=%d\n",
+  XSDebug(io.redirectValid, "update_req: pc=0x%x, hit=%d, misPred=%d, oldCtr=%d, taken=%d, target=0x%x, btbType=%d\n",
+    u.pc, u.hit, u.misPred, u.oldCtr, u.taken, u.target, u.btbType)
+  XSDebug(io.redirectValid, "update: noNeedToUpdate=%d, writeValid=%d, bank=%d, row=%d, newCtr=%d\n",
     noNeedToUpdate, btbWriteValid, updateBankIdx, updateRow, newCtr)
 }
\ No newline at end of file

src/main/scala/xiangshan/frontend/jbtac.scala

@@ -12,7 +12,7 @@ class JBTACUpdateBundle extends XSBundle {
   val fetchIdx = UInt(log2Up(PredictWidth).W)
   val hist = UInt(HistoryLength.W)
   val target = UInt(VAddrBits.W)
-  val _type = UInt(2.W)
+  val btbType = UInt(2.W)
   val misPred = Bool()
 }
 
@@ -98,7 +98,7 @@ class JBTAC extends XSModule {
 
   val writeBank = jbtacAddr.getBank(updateHistXORAddr)
   val writeRow = jbtacAddr.getBankIdx(updateHistXORAddr)
-  val writeValid = io.redirectValid && io.update.misPred && io.update._type === BTBtype.I
+  val writeValid = io.redirectValid && io.update.misPred && io.update.btbType === BTBtype.I
   for (b <- 0 until JbtacBanks) {
     when (b.U === writeBank) {
       jbtac(b).io.w.req.valid := writeValid
@@ -116,5 +116,5 @@ class JBTAC extends XSModule {
   XSDebug(nextFire, "[JBTAC]read_resp: pc=0x%x, bank=%d, row=%d, target=0x%x, offset=%d, hit=%d\n",
     io.in.pcLatch, readBankLatch, readRowLatch, readEntries(readBankLatch).target, readEntries(readBankLatch).offset, outHit)
   XSDebug(io.redirectValid, "[JBTAC]update_req: fetchPC=0x%x, writeValid=%d, hist=%b, bank=%d, row=%d, target=0x%x, offset=%d, type=0x%d\n",
-    io.update.fetchPC, writeValid, io.update.hist, writeBank, writeRow, io.update.target, io.update.fetchIdx, io.update._type)
+    io.update.fetchPC, writeValid, io.update.hist, writeBank, writeRow, io.update.target, io.update.fetchIdx, io.update.btbType)
 }
\ No newline at end of file