Merge branch 'master' of github.com:RISCVERS/XiangShan into l1plusCache

.github/workflows/emu.yml

@@ -70,7 +70,7 @@ jobs:
           echo $AM_HOME
           echo $NEMU_HOME
           echo $NOOP_HOME
-          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run
+          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run 2> /dev/null
 
   riscv-tests:
     runs-on: self-hosted
@@ -87,5 +87,5 @@ jobs:
           echo $NEMU_HOME
           echo $NOOP_HOME
           echo $RVTEST_HOME
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run
+          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run 2> /dev/null
 

.gitmodules

 [submodule "rocket-chip"]
 	path = rocket-chip
 	url = https://github.com/chipsalliance/rocket-chip.git
-	branch = 2bdb03dbca3f77ad4c378cc1b95ab4961bc1448a
+	branch = d6bd3c61993637c3f10544c59e861fae8af29f39
 [submodule "block-inclusivecache-sifive"]
 	path = block-inclusivecache-sifive
 	url = https://github.com/RISCVERS/block-inclusivecache-sifive.git
 	branch = 5491dcc937ed3c6f7722bef9db448653daab75e8
+[submodule "chiseltest"]
+	path = chiseltest
+	url = https://github.com/ucb-bar/chisel-testers2.git
+	branch = 3e3ecc5b25b7b6bc48341ec07c7a54b7ad53bcb7

Makefile

@@ -133,7 +133,7 @@ clean:
 
 init:
 	git submodule update --init
-	# do not use a recursive init to pull some not used submodules
+	@# do not use a recursive init to pull some not used submodules
 	cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat
 
 .PHONY: verilog emu clean help init $(REF_SO)

build.sc

@@ -5,7 +5,7 @@ import scalalib._
 import coursier.maven.MavenRepository
 
 object CustomZincWorkerModule extends ZincWorkerModule {
-  def repositories() = Seq(
+  def repositories() = super.repositories ++ Seq(
     MavenRepository("https://maven.aliyun.com/repository/public"),
     MavenRepository("https://maven.aliyun.com/repository/apache-snapshots")
   )
@@ -25,8 +25,8 @@ trait CommonModule extends ScalaModule {
   override def scalacPluginIvyDeps = Agg(macroParadise)
 }
 
-val rocketChisel = Agg(
-  ivy"edu.berkeley.cs::chisel3:3.3.1"
+val chisel = Agg(
+  ivy"edu.berkeley.cs::chisel3:3.4.0"
 )
 
 object `rocket-chip` extends SbtModule with CommonModule {
@@ -34,7 +34,7 @@ object `rocket-chip` extends SbtModule with CommonModule {
   override def ivyDeps = super.ivyDeps() ++ Agg(
     ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
     ivy"org.json4s::json4s-jackson:3.6.1"
-  ) ++ rocketChisel
+  ) ++ chisel
 
 
   object `api-config-chipsalliance` extends CommonModule {
@@ -44,7 +44,7 @@ object `rocket-chip` extends SbtModule with CommonModule {
   object macros extends SbtModule with CommonModule
 
   object hardfloat extends SbtModule with CommonModule {
-    override def ivyDeps = super.ivyDeps() ++ rocketChisel
+    override def ivyDeps = super.ivyDeps() ++ chisel
   }
 
   override def moduleDeps = super.moduleDeps ++ Seq(
@@ -54,30 +54,42 @@ object `rocket-chip` extends SbtModule with CommonModule {
 }
 
 object `block-inclusivecache-sifive` extends CommonModule {
-  override def ivyDeps = super.ivyDeps() ++ rocketChisel
+  override def ivyDeps = super.ivyDeps() ++ chisel
 
   override def millSourcePath = super.millSourcePath / 'design / 'craft / 'inclusivecache
 
   override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`)
 }
 
+object chiseltest extends CommonModule with SbtModule {
+  override def ivyDeps = super.ivyDeps() ++ Agg(
+	ivy"edu.berkeley.cs::treadle:1.3.0",
+	ivy"org.scalatest::scalatest:3.0.8",
+	ivy"com.lihaoyi::utest:0.7.4"
+  ) ++ chisel
+  object test extends Tests {
+	def ivyDeps = Agg(ivy"org.scalacheck::scalacheck:1.14.3")
+	def testFrameworks = Seq("org.scalatest.tools.Framework")
+  }
+}
+
 
 object XiangShan extends CommonModule with SbtModule {
   override def millSourcePath = millOuterCtx.millSourcePath
 
   override def forkArgs = Seq("-Xmx10G")
 
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    ivy"edu.berkeley.cs::chisel3:3.3.2"
+  override def ivyDeps = super.ivyDeps() ++ chisel
+  override def moduleDeps = super.moduleDeps ++ Seq(
+    `rocket-chip`, 
+	`block-inclusivecache-sifive`,
+	chiseltest
   )
 
-  override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`, `block-inclusivecache-sifive`)
-
   object test extends Tests {
     override def ivyDeps = super.ivyDeps() ++ Agg(
       ivy"org.scalatest::scalatest:3.0.4",
       ivy"edu.berkeley.cs::chisel-iotesters:1.2+",
-      ivy"edu.berkeley.cs::chiseltest:0.2.1"
     )
 
     def testFrameworks = Seq(

chiseltest @ 3e3ecc5b

+Subproject commit 3e3ecc5b25b7b6bc48341ec07c7a54b7ad53bcb7

rocket-chip @ d6bd3c61

-Subproject commit 2bdb03dbca3f77ad4c378cc1b95ab4961bc1448a
+Subproject commit d6bd3c61993637c3f10544c59e861fae8af29f39

src/main/scala/xiangshan/frontend/PreDecode.scala

@@ -14,7 +14,7 @@ trait HasPdconst{ this: XSModule =>
     val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
     val rd = Mux(isRVC(instr), instr(12), instr(11,7))
     val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
-    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd)
+    val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64
     val isRet = brType === BrType.jalr && isLink(rs) && !isCall
     List(brType, isCall, isRet)
   }

src/main/scala/xiangshan/frontend/RAS.scala

@@ -104,7 +104,7 @@ class RAS extends BasePredictor
     //update commit ras
     val commit_push = !commit_is_full && io.recover.valid && io.recover.bits.pd.isCall
     val commit_pop = !commit_is_empty && io.recover.valid && io.recover.bits.pd.isRet
-    val commit_new_addr = io.recover.bits.pc + 4.U  //TODO: consider RVC
+    val commit_new_addr = Mux(io.recover.bits.pd.isRVC,io.recover.bits.pc + 2.U,io.recover.bits.pc + 4.U) 
     val commit_ras_write = WireInit(0.U.asTypeOf(rasEntry()))
     val commit_alloc_new = commit_new_addr =/= commit_ras_top_addr
     when (commit_push) {
@@ -200,4 +200,4 @@ class RAS extends BasePredictor
     //     }
     // }
 
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala

@@ -300,6 +300,14 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
     }
   })
 
+  // move tailPtr
+  // allocatedMask: dequeuePtr can go to the next 1-bit
+  val allocatedMask = VecInit((0 until LoadQueueSize).map(i => allocated(i) || !enqDeqMask(i)))
+  // find the first one from deqPtr (ringBufferTail)
+  val nextTail1 = getFirstOneWithFlag(allocatedMask, tailMask, ringBufferTailExtended.flag)
+  val nextTail = Mux(Cat(allocatedMask).orR, nextTail1, ringBufferHeadExtended)
+  ringBufferTailExtended := nextTail
+
   // When load commited, mark it as !allocated, this entry will be recycled later
   (0 until CommitWidth).map(i => {
     when(loadCommit(i)) {
@@ -307,8 +315,6 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
       XSDebug("load commit %d: idx %d %x\n", i.U, mcommitIdx(i), uop(mcommitIdx(i)).cf.pc)
     }
   })
-  // move tailPtr
-  ringBufferTailExtended := ringBufferTailExtended + PopCount(loadCommit)
 
   // rollback check
   val rollback = Wire(Vec(StorePipelineWidth, Valid(new Redirect)))

src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala

@@ -180,6 +180,15 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     }
   })
 
+  // remove retired insts from sq, add retired store to sbuffer
+
+  // move tailPtr
+  // allocatedMask: dequeuePtr can go to the next 1-bit
+  val allocatedMask = VecInit((0 until StoreQueueSize).map(i => allocated(i) || !enqDeqMask(i)))
+  // find the first one from deqPtr (ringBufferTail)
+  val nextTail1 = getFirstOneWithFlag(allocatedMask, tailMask, ringBufferTailExtended.flag)
+  val nextTail = Mux(Cat(allocatedMask).orR, nextTail1, ringBufferHeadExtended)
+  ringBufferTailExtended := nextTail
 
   // load forward query
   // check over all lq entries and forward data from the first matched store
@@ -241,13 +250,13 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     }
   })
 
-  // remove retired insts from sq, add retired store to sbuffer
   val storeCommitSelVec = VecInit((0 until StoreQueueSize).map(i => {
     allocated(i) && commited(i)
   }))
   val (storeCommitValid, storeCommitSel) = selectFirstTwo(storeCommitSelVec, tailMask)
+  
+  // get no more than 2 commited store from storeCommitedQueue
   // send selected store inst to sbuffer
-  val dequeueValid = Wire(Vec(2, Bool()))
   (0 until 2).map(i => {
     val ptr = storeCommitSel(i)
     val mmio = data(ptr).mmio
@@ -263,14 +272,11 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     io.sbuffer(i).bits.meta.mask     := data(ptr).mask
     
     // update sq meta if store inst is send to sbuffer
-    dequeueValid(i) := storeCommitValid(i) && (mmio || io.sbuffer(i).ready)
-    when (dequeueValid(i)) {
+    when(storeCommitValid(i) && (mmio || io.sbuffer(i).ready)) {
       allocated(ptr) := false.B
     }
   })
-  // move tailPtr
-  ringBufferTailExtended := ringBufferTailExtended + PopCount(dequeueValid)
-
+  
   // Memory mapped IO / other uncached operations
   
   // setup misc mem access req

src/main/scala/xstransforms/ShowPrintTransform.scala

@@ -40,7 +40,7 @@ class ShowPrintTransform extends Transform with DependencyAPIMigration {
 
     def findSubModules(m: DefModule): Unit = {
       def viewStmt(s: Statement): Statement = s match {
-        case DefInstance(_, name, module) =>
+        case DefInstance(_, name, module, _) =>
           ancestors(module) = ancestors(m.name) + m.name
           queue += module
           s

src/test/csrc/emu.cpp

@@ -81,6 +81,9 @@ Emulator::Emulator(int argc, const char *argv[]):
   srand48(args.seed);
   Verilated::randReset(2);
 
+  // init core
+  reset_ncycles(10);
+
   // init ram
   extern void init_ram(const char *img);
   init_ram(args.image);
@@ -104,9 +107,6 @@ Emulator::Emulator(int argc, const char *argv[]):
   enable_waveform = false;
 #endif
 
-  // init core
-  reset_ncycles(10);
-
   if (args.snapshot_path != NULL) {
     printf("loading from snapshot `%s`...\n", args.snapshot_path);
     snapshot_load(args.snapshot_path);

src/test/csrc/ram.cpp

@@ -115,16 +115,15 @@ void init_ram(const char *img) {
   //new end
 }
 
-extern "C" void ram_helper(
-    uint64_t rIdx, uint64_t *rdata, uint64_t wIdx, uint64_t wdata, uint64_t wmask, uint8_t wen) {
+extern "C" uint64_t ram_read_helper(uint64_t rIdx) {
   if (rIdx >= RAMSIZE / sizeof(uint64_t)) {
     printf("ERROR: ram idx = 0x%x out of bound!\n", rIdx);
-    // TODO: don't allow out of bound when crossbar is ready
-    //assert(rIdx < RAMSIZE / sizeof(uint64_t));
-    *rdata = 0xabcd12345678dcbaUL;
-    return;
+    assert(rIdx < RAMSIZE / sizeof(uint64_t));
   }
-  *rdata = ram[rIdx];
+  return ram[rIdx];
+}
+
+extern "C" void ram_write_helper(uint64_t wIdx, uint64_t wdata, uint64_t wmask, uint8_t wen) {
   if (wen) {
     assert(wIdx < RAMSIZE / sizeof(uint64_t));
     ram[wIdx] = (ram[wIdx] & ~wmask) | (wdata & wmask);

src/test/scala/cache/L2CacheTest.scala

@@ -5,6 +5,7 @@ import chisel3._
 import chisel3.util._
 import chiseltest.experimental.TestOptionBuilder._
 import chiseltest.internal.VerilatorBackendAnnotation
+import chiseltest.internal.LineCoverageAnnotation
 import chiseltest._
 import chisel3.experimental.BundleLiterals._
 import firrtl.stage.RunFirrtlTransformAnnotation
@@ -257,6 +258,7 @@ class L2CacheTest extends FlatSpec with ChiselScalatestTester with Matchers{
 
   val annos = Seq(
     VerilatorBackendAnnotation,
+    LineCoverageAnnotation,
     RunFirrtlTransformAnnotation(new PrintModuleName)
   )
 

src/test/vsrc/ram.v

-import "DPI-C" function void ram_helper
+import "DPI-C" function void ram_write_helper
 (
-  input  longint    rIdx,
-  output longint    rdata,
   input  longint    wIdx,
   input  longint    wdata,
   input  longint    wmask,
   input  bit    wen
 );
 
+import "DPI-C" function longint ram_read_helper
+(
+  input  longint    rIdx
+);
+
 module RAMHelper(
   input         clk,
   input  [63:0] rIdx,
@@ -18,8 +21,10 @@ module RAMHelper(
   input         wen
 );
 
+  assign rdata = ram_read_helper(rIdx);
+
   always @(posedge clk) begin
-    ram_helper(rIdx, rdata, wIdx, wdata, wmask, wen);
+    ram_write_helper(wIdx, wdata, wmask, wen);
   end
 
 endmodule