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体验新版 GitCode,发现更多精彩内容 >>
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91d2c8b2
编写于
11月 04, 2019
作者:
W
William Wang
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
fix(CSR): fix sstatus mask
上级
521115bb
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
27 addition
and
24 deletion
+27
-24
src/main/scala/noop/IDU.scala
src/main/scala/noop/IDU.scala
+3
-3
src/main/scala/noop/NOOP.scala
src/main/scala/noop/NOOP.scala
+14
-5
src/main/scala/noop/fu/CSR.scala
src/main/scala/noop/fu/CSR.scala
+9
-15
src/main/scala/utils/Debug.scala
src/main/scala/utils/Debug.scala
+1
-1
未找到文件。
src/main/scala/noop/IDU.scala
浏览文件 @
91d2c8b2
...
@@ -288,9 +288,9 @@ class IDU extends NOOPModule with HasInstrType {
...
@@ -288,9 +288,9 @@ class IDU extends NOOPModule with HasInstrType {
// val crossLineJump = state === s_waitnext && fuType === FuType.alu && fuOpType.isBru()
// val crossLineJump = state === s_waitnext && fuType === FuType.alu && fuOpType.isBru()
Debug
(){
Debug
(){
//
when(io.out.fire()){
when
(
io
.
out
.
fire
()){
//
printf("[IDU] pc %x pcin: %x instr %x instrin %x state %x instrType: %x fuType: %x fuOpType: %x brIdx: %x npcin: %x npcout: %x valid: %x\n", pcOut, io.in.bits.pc, instr, io.in.bits.instr, state, instrType, fuType, fuOpType, brIdx, io.in.bits.pnpc, pnpcOut, io.out.fire())
printf
(
"[IDU] pc %x pcin: %x instr %x instrin %x state %x instrType: %x fuType: %x fuOpType: %x brIdx: %x npcin: %x npcout: %x valid: %x\n"
,
pcOut
,
io
.
in
.
bits
.
pc
,
instr
,
io
.
in
.
bits
.
instr
,
state
,
instrType
,
fuType
,
fuOpType
,
brIdx
,
io
.
in
.
bits
.
pnpc
,
pnpcOut
,
io
.
out
.
fire
())
//
}
}
}
}
// io.out.bits.cf <> io.in.bits
// io.out.bits.cf <> io.in.bits
...
...
src/main/scala/noop/NOOP.scala
浏览文件 @
91d2c8b2
...
@@ -71,11 +71,20 @@ class NOOP(implicit val p: NOOPConfig) extends NOOPModule {
...
@@ -71,11 +71,20 @@ class NOOP(implicit val p: NOOPConfig) extends NOOPModule {
ifu
.
io
.
flushVec
.
asUInt
,
ifu
.
io
.
out
.
valid
,
ifu
.
io
.
out
.
ready
,
ifu
.
io
.
flushVec
.
asUInt
,
ifu
.
io
.
out
.
valid
,
ifu
.
io
.
out
.
ready
,
idu
.
io
.
in
.
valid
,
idu
.
io
.
in
.
ready
,
isu
.
io
.
in
.
valid
,
isu
.
io
.
in
.
ready
,
idu
.
io
.
in
.
valid
,
idu
.
io
.
in
.
ready
,
isu
.
io
.
in
.
valid
,
isu
.
io
.
in
.
ready
,
exu
.
io
.
in
.
valid
,
exu
.
io
.
in
.
ready
,
wbu
.
io
.
in
.
valid
,
wbu
.
io
.
in
.
ready
)
exu
.
io
.
in
.
valid
,
exu
.
io
.
in
.
ready
,
wbu
.
io
.
in
.
valid
,
wbu
.
io
.
in
.
ready
)
when
(
ifu
.
io
.
out
.
valid
)
{
printf
(
"IFU: pc = 0x%x, instr = 0x%x, pnpc = 0x%x"
,
ifu
.
io
.
out
.
bits
.
pc
,
ifu
.
io
.
out
.
bits
.
instr
,
ifu
.
io
.
out
.
bits
.
pnpc
)
;
printf
(
p
"IFUO: redirectIO:${ifu.io.out.bits.redirect}\n"
)
;
printf
(
"IFUO: exceptionVec: %x\n"
,
ifu
.
io
.
out
.
bits
.
exceptionVec
.
asUInt
)}
when
(
ifu
.
io
.
out
.
valid
)
{
printf
(
"IFU: pc = 0x%x, instr = 0x%x, pnpc = 0x%x\n"
,
ifu
.
io
.
out
.
bits
.
pc
,
ifu
.
io
.
out
.
bits
.
instr
,
ifu
.
io
.
out
.
bits
.
pnpc
)}
;
when
(
idu
.
io
.
in
.
valid
)
{
printf
(
"IDU: pc = 0x%x, instr = 0x%x, pnpc = 0x%x\n"
,
idu
.
io
.
in
.
bits
.
pc
,
idu
.
io
.
in
.
bits
.
instr
,
idu
.
io
.
in
.
bits
.
pnpc
)
;
printf
(
p
"IDUO: redirectIO:${idu.io.out.bits.cf.redirect} redirectIOC:${idu.io.redirect}\n"
)
;
printf
(
"IDUO: exceptionVec:%x\n"
,
idu
.
io
.
out
.
bits
.
cf
.
exceptionVec
.
asUInt
)}
when
(
idu
.
io
.
in
.
valid
)
{
printf
(
"IBF: pc = 0x%x, instr = 0x%x, pnpc = 0x%x\n"
,
idu
.
io
.
in
.
bits
.
pc
,
idu
.
io
.
in
.
bits
.
instr
,
idu
.
io
.
in
.
bits
.
pnpc
)}
;
when
(
isu
.
io
.
in
.
valid
)
{
printf
(
"ISU: pc = 0x%x, pnpc = 0x%x\n"
,
isu
.
io
.
in
.
bits
.
cf
.
pc
,
isu
.
io
.
in
.
bits
.
cf
.
pnpc
)
;
printf
(
p
"ISUO: ${isu.io.out.bits.cf.redirect}\n"
)
;
printf
(
"ISUO: exceptionVec:%x\n"
,
isu
.
io
.
out
.
bits
.
cf
.
exceptionVec
.
asUInt
)}
when
(
idu
.
io
.
out
.
valid
)
{
printf
(
"IDU: pc = 0x%x, instr = 0x%x, pnpc = 0x%x\n"
,
idu
.
io
.
out
.
bits
.
cf
.
pc
,
idu
.
io
.
out
.
bits
.
cf
.
instr
,
idu
.
io
.
out
.
bits
.
cf
.
pnpc
)}
;
when
(
exu
.
io
.
in
.
valid
)
{
printf
(
"EXU: pc = 0x%x, pnpc = 0x%x\n"
,
exu
.
io
.
in
.
bits
.
cf
.
pc
,
exu
.
io
.
in
.
bits
.
cf
.
pnpc
)
;
printf
(
p
"EXUO: ${exu.io.out.bits.decode.cf.redirect}\n"
)
;
printf
(
"EXUO: exceptionVecIn:%x\n"
,
exu
.
io
.
in
.
bits
.
cf
.
exceptionVec
.
asUInt
)}
when
(
isu
.
io
.
in
.
valid
)
{
printf
(
"ISU: pc = 0x%x, pnpc = 0x%x\n"
,
isu
.
io
.
in
.
bits
.
cf
.
pc
,
isu
.
io
.
in
.
bits
.
cf
.
pnpc
)}
;
when
(
wbu
.
io
.
in
.
valid
)
{
printf
(
"WBU: pc = 0x%x rfWen:%d rfDest:%d rfData:%x Futype:%x commits(0):%x commits(1):%x commits(3):%x\n"
,
wbu
.
io
.
in
.
bits
.
decode
.
cf
.
pc
,
wbu
.
io
.
in
.
bits
.
decode
.
ctrl
.
rfWen
,
wbu
.
io
.
in
.
bits
.
decode
.
ctrl
.
rfDest
,
wbu
.
io
.
wb
.
rfData
,
wbu
.
io
.
in
.
bits
.
decode
.
ctrl
.
fuType
,
wbu
.
io
.
in
.
bits
.
commits
(
0
),
wbu
.
io
.
in
.
bits
.
commits
(
1
),
wbu
.
io
.
in
.
bits
.
commits
(
3
))
}
when
(
exu
.
io
.
in
.
valid
)
{
printf
(
"EXU: pc = 0x%x, pnpc = 0x%x\n"
,
exu
.
io
.
in
.
bits
.
cf
.
pc
,
exu
.
io
.
in
.
bits
.
cf
.
pnpc
)}
;
when
(
wbu
.
io
.
in
.
valid
)
{
printf
(
"WBU: pc = 0x%x rfWen:%d rfDest:%d rfData:%x Futype:%x\n"
,
wbu
.
io
.
in
.
bits
.
decode
.
cf
.
pc
,
wbu
.
io
.
in
.
bits
.
decode
.
ctrl
.
rfWen
,
wbu
.
io
.
in
.
bits
.
decode
.
ctrl
.
rfDest
,
wbu
.
io
.
wb
.
rfData
,
wbu
.
io
.
in
.
bits
.
decode
.
ctrl
.
fuType
)}
// when (io.in.valid) { printf("TIMER: %d WBU: pc = 0x%x wen %x wdata %x mmio %x intrNO %x\n", GTimer(), io.in.bits.decode.cf.pc, io.wb.rfWen, io.wb.rfData, io.in.bits.isMMIO, io.in.bits.intrNO) }
// printf(p"IFUO: redirectIO:${ifu.io.out.bits.redirect}\n") ; printf("IFUO: exceptionVec: %x\n", ifu.io.out.bits.exceptionVec.asUInt)}
// printf(p"IDUO: redirectIO:${idu.io.out.bits.cf.redirect} redirectIOC:${idu.io.redirect}\n") ; printf("IDUO: exceptionVec:%x\n", idu.io.out.bits.cf.exceptionVec.asUInt)}
// printf(p"ISUO: ${isu.io.out.bits.cf.redirect}\n") ; printf("ISUO: exceptionVec:%x\n", isu.io.out.bits.cf.exceptionVec.asUInt)}
// printf(p"EXUO: ${exu.io.out.bits.decode.cf.redirect}\n") ; printf("EXUO: exceptionVecIn:%x\n", exu.io.in.bits.cf.exceptionVec.asUInt)}
// when (wbu.io.in.valid) { printf("WBU: pc = 0x%x rfWen:%d rfDest:%d rfData:%x Futype:%x commits(0):%x commits(1):%x commits(3):%x\n", wbu.io.in.bits.decode.cf.pc, wbu.io.in.bits.decode.ctrl.rfWen, wbu.io.in.bits.decode.ctrl.rfDest, wbu.io.wb.rfData, wbu.io.in.bits.decode.ctrl.fuType, wbu.io.in.bits.commits(0), wbu.io.in.bits.commits(1), wbu.io.in.bits.commits(3)) }
}
}
isu
.
io
.
wb
<>
wbu
.
io
.
wb
isu
.
io
.
wb
<>
wbu
.
io
.
wb
...
...
src/main/scala/noop/fu/CSR.scala
浏览文件 @
91d2c8b2
...
@@ -235,25 +235,19 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst{
...
@@ -235,25 +235,19 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst{
// Superviser-Level CSRs
// Superviser-Level CSRs
// val sstatus = RegInit(UInt(XLEN.W), "h00000000".U)
// val sstatus = RegInit(UInt(XLEN.W), "h00000000".U)
val
sstatusWmask
=
"h
18014
2"
.
U
val
sstatusWmask
=
"h
c012
2"
.
U
// Sstatus Write Mask
// Sstatus Write Mask
// -------------------------------------------------------
// -------------------------------------------------------
// 20 19 9 6 2
// 19 9 5 2
// 1 1000 0000 0001 0100 0010
// 0 1100 0000 0001 0010 0010
// 1 8 0 1 4 2
// 0 c 0 1 2 2
// -------------------------------------------------------
val
sstatusRmask
=
"h100000030019d142"
.
U
// Sstatus Read Mask
// -------------------------------------------------------
// 32 20 19 9 6 2
// 1 0 0 0 0 0 0 3 0 0 0001 1001 1110 0001 0100 0010
// 1 0 0 0 0 0 0 3 0 0 1 9 d 1 4 2
// -------------------------------------------------------
// -------------------------------------------------------
val
sstatusRmask
=
"h80000003000de122"
.
U
// Sstatus Read Mask = (SSTATUS_WMASK | (0xf << 13) | (1ull << 63) | (3ull << 32))
val
stvec
=
RegInit
(
UInt
(
XLEN
.
W
),
0.
U
)
val
stvec
=
RegInit
(
UInt
(
XLEN
.
W
),
0.
U
)
// val sie = RegInit(0.U(XLEN.W))
// val sie = RegInit(0.U(XLEN.W))
val
sieWmask
=
"h333"
.
U
val
sieMask
=
"h333"
.
U
&
mideleg
val
sieRmask
=
"h333"
.
U
val
sipMask
=
"h103"
.
U
&
mideleg
val
sipMask
=
"h103"
.
U
//val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U)
//val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U)
val
satp
=
RegInit
(
UInt
(
XLEN
.
W
),
0.
U
)
val
satp
=
RegInit
(
UInt
(
XLEN
.
W
),
0.
U
)
io
.
satp
:=
satp
io
.
satp
:=
satp
...
@@ -312,7 +306,7 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst{
...
@@ -312,7 +306,7 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst{
// MaskedRegMap(Sedeleg, Sedeleg),
// MaskedRegMap(Sedeleg, Sedeleg),
// MaskedRegMap(Sideleg, Sideleg),
// MaskedRegMap(Sideleg, Sideleg),
MaskedRegMap
(
Sie
,
mie
,
sie
Wmask
&
mideleg
,
MaskedRegMap
.
NoSideEffect
,
sieRm
ask
),
MaskedRegMap
(
Sie
,
mie
,
sie
Mask
,
MaskedRegMap
.
NoSideEffect
,
sieM
ask
),
MaskedRegMap
(
Stvec
,
stvec
),
MaskedRegMap
(
Stvec
,
stvec
),
// MaskedRegMap(Scounteren, Scounteren),
// MaskedRegMap(Scounteren, Scounteren),
...
...
src/main/scala/utils/Debug.scala
浏览文件 @
91d2c8b2
...
@@ -7,7 +7,7 @@ import noop.NOOPConfig
...
@@ -7,7 +7,7 @@ import noop.NOOPConfig
object
Debug
{
object
Debug
{
def
apply
(
flag
:
Boolean
=
NOOPConfig
().
EnableDebug
,
cond
:
Bool
=
true
.
B
)(
body
:
=>
Unit
)
:
Any
=
def
apply
(
flag
:
Boolean
=
NOOPConfig
().
EnableDebug
,
cond
:
Bool
=
true
.
B
)(
body
:
=>
Unit
)
:
Any
=
if
(
flag
)
{
when
(
cond
&&
GTimer
()
>
56
553
00.
U
)
{
body
}
}
if
(
flag
)
{
when
(
cond
&&
GTimer
()
>
56
460
00.
U
)
{
body
}
}
}
}
object
ShowType
{
object
ShowType
{
...
...
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