Regfile: convert diff test reg to ieee fmt

907bf7ec · LinJiawei · 1c0c19cd · 907bf7ec
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Showing with 5 addition and 1 deletion

src/main/scala/xiangshan/backend/regfile/Regfile.scala src/main/scala/xiangshan/backend/regfile/Regfile.scala +5 -1

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--- a/src/main/scala/xiangshan/backend/regfile/Regfile.scala
+++ b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
@@ -54,7 +54,11 @@ class Regfile
      )

      val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(
-        x => if(hasZero && x._2==0) 0.U else mem(x._1)
+        x => if(hasZero){
+          if(x._2 == 0) 0.U else mem(x._1)
+        } else {
+          ieee(mem(x._1))
+        }
      )))
      ExcitingUtils.addSource(
        debugArchReg,