diff --git a/src/main/scala/xiangshan/backend/regfile/Regfile.scala b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
index 2200c88d36fdaac25f7ccae0462a48e2b1eb811d..033523f4e158fc53755ee81600319dcbaa5831b9 100644
--- a/src/main/scala/xiangshan/backend/regfile/Regfile.scala
+++ b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
@@ -54,7 +54,11 @@ class Regfile
       )
 
       val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(
-        x => if(hasZero && x._2==0) 0.U else mem(x._1)
+        x => if(hasZero){
+          if(x._2 == 0) 0.U else mem(x._1)
+        } else {
+          ieee(mem(x._1))
+        }
       )))
       ExcitingUtils.addSource(
         debugArchReg,