PrintModuleName: must run after wiring transform

debug/Makefile

@@ -95,11 +95,10 @@ disassemble-xv6:
 	cp $(XV6_HOME)/build/code.txt ./d-xv6.log
 
 
-P = 4
-SUITE = xiangshan.backend.exu.AluTest
+SUITE = cache.L2CacheTest
 
 unit-test:
-	cd .. && mill XiangShan.test.testOnly -o -s $(SUITE) -P$(P)
+	cd .. && mill XiangShan.test.testOnly -o -s $(SUITE)
 
 unit-test-all:
 	cd .. && mill XiangShan.test.test -P$(P)

src/main/scala/xstransforms/PrintModuleName.scala

@@ -2,6 +2,9 @@ package xstransforms
 
 import firrtl._
 import firrtl.ir._
+import firrtl.options.Dependency
+import firrtl.passes.wiring.WiringTransform
+import firrtl.stage.TransformManager.TransformDependency
 import utils.XSLog
 
 class PrintModuleName extends Transform with DependencyAPIMigration {
@@ -9,6 +12,7 @@ class PrintModuleName extends Transform with DependencyAPIMigration {
   // avoid print's check
   override def prerequisites = firrtl.stage.Forms.Checks
   override def invalidates(a: Transform) = false
+  override def optionalPrerequisites = Seq(Dependency[WiringTransform])
 
   override protected def execute(state: CircuitState): CircuitState = {
 

src/test/scala/cache/L2CacheTest.scala

@@ -255,6 +255,11 @@ class L2CacheTest extends FlatSpec with ChiselScalatestTester with Matchers{
 
   top.Parameters.set(top.Parameters.debugParameters)
 
+  val annos = Seq(
+    VerilatorBackendAnnotation,
+    RunFirrtlTransformAnnotation(new PrintModuleName)
+  )
+
   it should "run" in {
 
     implicit val p = Parameters((site, up, here) => {
@@ -264,16 +269,8 @@ class L2CacheTest extends FlatSpec with ChiselScalatestTester with Matchers{
         L3CacheTestParams()
     })
 
-    /*
-    test(LazyModule(new L2TestTopWrapper()).module)
-      .withAnnotations(Seq(
-        VerilatorBackendAnnotation,
-        RunFirrtlTransformAnnotation(new PrintModuleName)
-      )){ c =>
-        */
-
-    test(LazyModule(new L2TestTopWrapper()).module)
-      .withAnnotations(Seq(VerilatorBackendAnnotation)){ c =>
+     test(LazyModule(new L2TestTopWrapper()).module)
+      .withAnnotations(annos){ c =>
 
         c.io.in.initSource().setSourceClock(c.clock)
         c.io.out.initSink().setSinkClock(c.clock)