fix bug: add ready signal in tlb module. when tlb is at reset-state, stall

src/main/scala/noop/Cache.scala

@@ -39,7 +39,7 @@ sealed trait HasCacheConst {
   val WordIndexBits = log2Up(LineBeats)
   val TagBits = AddrBits - OffsetBits - IndexBits
 
-  val debug = true && cacheName == "dcache"
+  val debug = true //&& cacheName == "icache"
 
   def addrBundle = new Bundle {
     val tag = UInt(TagBits.W)
@@ -369,8 +369,8 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
   Debug() {
     if(debug) {
     when(true.B) {
-      printf("%d: [" + cacheName + " S3]: out.valid:%d rdata:%x cmd:%d user:%x \n", 
-      GTimer(), io.out.valid, io.out.bits.rdata, io.out.bits.cmd, io.out.bits.user.getOrElse(0.U))
+      when(io.in.valid) { printf("%d: [" + cacheName + " S3]: out.valid:%d rdata:%x cmd:%d user:%x \n", 
+      GTimer(), io.out.valid, io.out.bits.rdata, io.out.bits.cmd, io.out.bits.user.getOrElse(0.U)) }
       //printf("%d: [" + cacheName + " S3]: DHW: (%d, %d), data:%x MHW:(%d, %d)\n", 
       //GTimer(), dataHitWriteBus.req.valid, dataHitWriteBus.req.ready, dataHitWriteBus.req.bits.data.asUInt, metaHitWriteBus.req.valid, metaHitWriteBus.req.ready)
       //printf("%d: [" + cacheName + " S3]: useFD:%d isFD:%d FD:%x DreadArray:%x dataRead:%x inwaymask:%x FDwaymask:%x \n", 

src/main/scala/noop/TLB.scala

@@ -146,7 +146,7 @@ sealed trait HasTlbConst extends Sv39Const{
   val metaLen = vpnLen + asidLen + maskLen + flagLen // 27 + 16 + 18 + 8 = 69
   val dataLen = ppnLen + AddrBits // 44 + 64 = 108
 
-  val debug = true && tlbname == "dtlb"
+  val debug = true && tlbname == "itlb"
 
   def metaBundle = new Bundle {
     val vpn = UInt(vpnLen.W)
@@ -177,6 +177,8 @@ class TLBMeta(implicit val tlbConfig: TLBConfig) extends TlbModule { //TODO: ano
       val mask = Input(UInt(maskLen.W))
       val flag = Input(UInt(flagLen.W))
     }
+
+    val ready = Output(Bool())
   })
 
   val metas = Reg(Vec(NTLB, UInt(metaLen.W)))
@@ -202,6 +204,7 @@ class TLBMeta(implicit val tlbConfig: TLBConfig) extends TlbModule { //TODO: ano
 
   when (wen) { metas(dest) := data }
 
+  io.ready := !resetState
   def rready() = !resetState
   def wready() = !resetState
 }
@@ -297,7 +300,7 @@ class TLB(implicit val tlbConfig: TLBConfig) extends TlbModule{
       io.in.resp.valid := true.B
       io.in.resp.bits.rdata := 0.U
       io.in.resp.bits.cmd := SimpleBusCmd.readLast
-      io.in.resp.bits.user.map(_ := io.in.req.bits.user.getOrElse(0.U))
+      io.in.resp.bits.user.map(_ := tlbExec.io.in.bits.user.getOrElse(0.U))
       io.ipf := tlbExec.io.ipf
     }
   }
@@ -543,7 +546,7 @@ class TLBExec(implicit val tlbConfig: TLBConfig) extends TlbModule{
   io.out.bits.addr := Mux(hit, maskPaddr(hitData.ppn, req.addr, hitMask), maskPaddr(memRespStore.asTypeOf(pteBundle).ppn, req.addr, missMaskStore))
   io.out.valid := io.in.valid && Mux(hit && !hitWB, true.B , state === s_wait_resp)// && !alreadyOutFire
   
-  io.in.ready := io.out.ready && (state === s_idle) && !miss && !hitWB //maybe be optimized
+  io.in.ready := io.out.ready && (state === s_idle) && !miss && !hitWB && metasTLB.io.ready//maybe be optimized
 
   io.ipf := Mux(hit, hitinstrPF, missIPF)
   io.isFinish := io.out.fire() || io.pf.isPF()

src/main/scala/utils/Debug.scala

@@ -7,7 +7,7 @@ import noop.NOOPConfig
 
 object Debug {
   def apply(flag: Boolean = NOOPConfig().EnableDebug, cond: Bool = true.B)(body: => Unit): Any =
-    if (flag) { when (cond && GTimer() > 3220300.U) { body } }
+    if (flag) { when (cond && GTimer() > 111381250.U) { body } }
 }
 
 object ShowType {