device,AXI4Timer: support mtime and mtimecmp

src/main/scala/device/AXI4Timer.scala

@@ -6,9 +6,25 @@ import chisel3.util._
 import bus.axi4._
 import utils._
 
-class AXI4Timer extends AXI4SlaveModule(new AXI4Lite) {
-  val clk = 40000 // 40MHz / 1000
+class TimerIO extends Bundle {
+  val mtip = Output(Bool())
+}
+
+class AXI4Timer(sim: Boolean = false) extends AXI4SlaveModule(new AXI4Lite, new TimerIO) {
+  val mtime = RegInit(0.U(64.W))  // unit: ms
+  val mtimecmp = RegInit(0.U(64.W))
+
+  val clk = (if (!sim) 40000 /* 40MHz / 1000 */ else 2000)
   val tick = Counter(true.B, clk)._2
-  val ms = Counter(tick, 0x40000000)._1
-  in.r.bits.data := ms
+  when (tick) { mtime := mtime + 1.U }
+
+  val mapping = Map(
+    RegMap(0x0, mtime),
+    RegMap(0x8, mtimecmp)
+  )
+
+  RegMap.generate(mapping, raddr(3,0), in.r.bits.data,
+    waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
+
+  io.extra.get.mtip := mtime >= mtimecmp
 }

src/test/scala/top/SimMMIO.scala

@@ -35,7 +35,7 @@ class SimMMIO extends Module {
   xbar.io.in(0) <> io.rw
 
   val uart = Module(new AXI4UART)
-  val timer = Module(new AXI4Timer)
+  val timer = Module(new AXI4Timer(sim = true))
   val vga = Module(new AXI4VGA(sim = true))
   uart.io.in <> xbar.io.out(0).toAXI4Lite()
   timer.io.in <> xbar.io.out(1).toAXI4Lite()