Merge remote-tracking branch 'origin/dev-frontend' into dev-bpu-pipeline-rebase

.github/workflows/emu.yml

@@ -36,7 +36,7 @@ jobs:
           echo $AM_HOME
           echo $NEMU_HOME
           echo $NOOP_HOME
-          make -C $AM_HOME/tests/cputest/ ARCH=riscv64-noop V=OFF AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
+          make -C $AM_HOME/tests/cputest/ ARCH=riscv64-noop B=0 E=0 AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
 
   riscv-tests:
     runs-on: self-hosted
@@ -53,4 +53,4 @@ jobs:
           echo $NEMU_HOME
           echo $NOOP_HOME
           echo $RVTEST_HOME
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um V=OFF NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run
+          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um B=0 E=0 NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run

Makefile

@@ -103,13 +103,12 @@ SEED = -s $(shell seq 1 10000 | shuf | head -n 1)
 # use 'emu -h' to see more details
 B ?= 0
 E ?= -1
-V ?= ALL
 
 emu: $(EMU)
 ifeq ($(REMOTE),localhost)
-	@$(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E) -v $(V)
+	@$(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E)
 else
-	ssh $(REMOTE) "cd $(REMOTE_PREFIX) && $(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E) -v $(V)"
+	ssh $(REMOTE) "cd $(REMOTE_PREFIX) && $(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E)"
 endif
 
 cache:

debug/Makefile

@@ -3,8 +3,9 @@ NANOS_HOME ?= $(AM_HOME)/../nanos-lite
 SINGLETEST = ALL=min3
 
 B ?= 0
-E ?= -1
+E ?= 0
 V ?= ALL
+#V ?= OFF
 EMU_ARGS = B=$(B) E=$(E) V=$(V)
 
 # ------------------------------------------------------------------
@@ -12,14 +13,15 @@ EMU_ARGS = B=$(B) E=$(E) V=$(V)
 # ------------------------------------------------------------------
 
 cpu:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=dummy $(EMU_ARGS) run 2>&1 | tee cpu.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=add-longlong $(EMU_ARGS) run 2>&1 | tee > cpu.log
 
 # ------------------------------------------------------------------
 # run different test sets
 # ------------------------------------------------------------------
 
 cputest:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) run 2>&1 | tee cpu.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(EMU_ARGS) run 2>&1 | tee > cpu.log
+	cat cpu.log | grep different
 
 # bputest:
 # 	$(MAKE) -C $(AM_HOME)/tests/bputest $(ARCH) run 2>&1 | tee > bpu.log

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -176,14 +176,15 @@ class Brq extends XSModule {
       stateQueue(wbIdx) := s_wb
       brQueue(wbIdx).exuOut := exuWb.bits
       brQueue(wbIdx).misPred := brQueue(wbIdx).npc =/= exuWb.bits.redirect.target
-      brQueue(wbIdx).exuOut.redirect.hist := exuWb.bits.uop.cf.hist
+      // brQueue(wbIdx).exuOut.redirect.hist := exuWb.bits.uop.cf.hist
       // brQueue(wbIdx).exuOut.redirect.btbVictimWay := exuWb.bits.uop.cf.btbVictimWay
-      brQueue(wbIdx).exuOut.redirect.btbPredCtr := exuWb.bits.uop.cf.btbPredCtr
-      brQueue(wbIdx).exuOut.redirect.btbHitWay := exuWb.bits.uop.cf.btbHitWay
-      brQueue(wbIdx).exuOut.redirect.tageMeta := exuWb.bits.uop.cf.tageMeta
-      brQueue(wbIdx).exuOut.redirect.rasSp := exuWb.bits.uop.cf.rasSp
-      brQueue(wbIdx).exuOut.redirect.rasTopCtr := exuWb.bits.uop.cf.rasTopCtr
-      brQueue(wbIdx).exuOut.redirect.fetchIdx := exuWb.bits.uop.cf.fetchOffset << 2.U
+      // brQueue(wbIdx).exuOut.redirect.btbPredCtr := exuWb.bits.uop.cf.btbPredCtr
+      // brQueue(wbIdx).exuOut.redirect.btbHitWay := exuWb.bits.uop.cf.btbHitWay
+      // brQueue(wbIdx).exuOut.redirect.tageMeta := exuWb.bits.uop.cf.tageMeta
+      // brQueue(wbIdx).exuOut.redirect.rasSp := exuWb.bits.uop.cf.rasSp
+      // brQueue(wbIdx).exuOut.redirect.rasTopCtr := exuWb.bits.uop.cf.rasTopCtr
+      // brQueue(wbIdx).exuOut.redirect.fetchIdx := exuWb.bits.uop.cf.fetchOffset << 2.U
+      brQueue(wbIdx).exuOut.redirect := exuWb.bits.redirect
     }
   }
 
@@ -221,16 +222,17 @@ class Brq extends XSModule {
 
   XSInfo(debug_roq_redirect, "roq redirect, flush brq\n")
   XSInfo(debug_brq_redirect, p"brq redirect, target:${Hexadecimal(io.redirect.bits.target)} flptr:${io.redirect.bits.freelistAllocPtr}\n")
-
-  BoringUtils.addSource(io.out.fire(), "MbpInstr")
-  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred, "MbpRight")
-  BoringUtils.addSource(io.out.fire() && commitEntry.misPred, "MbpWrong")
-  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B, "MbpBRight")
-  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B, "MbpBWrong")
-  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J, "MbpJRight")
-  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J, "MbpJWrong")
-  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I, "MbpIRight")
-  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I, "MbpIWrong")
-  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R, "MbpRRight")
-  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R, "MbpRWrong")
+  if(EnableBPU){
+    BoringUtils.addSource(io.out.fire(), "MbpInstr")
+    BoringUtils.addSource(io.out.fire() && !commitEntry.misPred, "MbpRight")
+    BoringUtils.addSource(io.out.fire() && commitEntry.misPred, "MbpWrong")
+    BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B, "MbpBRight")
+    BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B, "MbpBWrong")
+    BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J, "MbpJRight")
+    BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J, "MbpJWrong")
+    BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I, "MbpIRight")
+    BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I, "MbpIWrong")
+    BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R, "MbpRRight")
+    BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R, "MbpRWrong")
+  }
 }
\ No newline at end of file

src/main/scala/xiangshan/backend/exu/AluExeUnit.scala

@@ -54,21 +54,29 @@ class AluExeUnit extends Exu(Exu.aluExeUnitCfg) {
   val target = Mux(isBranch, pc + offset, adderRes)(VAddrBits-1,0)
   val isRVC = uop.cf.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U)
 
-  //TODO fix me
-  io.out.bits.redirect := DontCare
 
   io.in.ready := io.out.ready
   val pcLatchSlot = Mux(isRVC, pc + 2.U, pc + 4.U)
   io.out.bits.redirectValid := io.out.valid && isBru//isBranch
+  io.out.bits.redirect.pc := uop.cf.pc
   io.out.bits.redirect.target := Mux(!taken && isBranch, pcLatchSlot, target)
   io.out.bits.redirect.brTarget := target
-  io.out.bits.redirect.taken := isBranch && taken
-  io.out.bits.redirect._type := "b00".U
   io.out.bits.redirect.brTag := uop.brTag
+  io.out.bits.redirect._type := "b00".U  
+  io.out.bits.redirect.taken := isBranch && taken
+  io.out.bits.redirect.hist := uop.cf.hist
+  io.out.bits.redirect.tageMeta := uop.cf.tageMeta
+  io.out.bits.redirect.fetchIdx := uop.cf.fetchOffset >> 2.U  //TODO: consider RVC
+  io.out.bits.redirect.btbVictimWay := uop.cf.btbVictimWay
+  io.out.bits.redirect.btbPredCtr := uop.cf.btbPredCtr
+  io.out.bits.redirect.btbHitWay := uop.cf.btbHitWay
+  io.out.bits.redirect.rasSp := uop.cf.rasSp
+  io.out.bits.redirect.rasTopCtr := uop.cf.rasTopCtr
   io.out.bits.redirect.isException := DontCare // false.B
   io.out.bits.redirect.roqIdx := uop.roqIdx
   io.out.bits.redirect.freelistAllocPtr := uop.freelistAllocPtr
 
+
   io.out.valid := valid
   io.out.bits.uop <> io.in.bits.uop
   io.out.bits.data := Mux(isJump, pcLatchSlot, aluRes)

src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala

@@ -36,17 +36,22 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
   val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U)
   val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
 
-  //TODO fix me
-  io.out.bits.redirect := DontCare
 
   io.out.bits.redirectValid := valid && isJUMP
-  io.out.bits.redirect.pc := io.in.bits.uop.cf.pc
+  io.out.bits.redirect.pc := uop.cf.pc
   io.out.bits.redirect.target := target
   io.out.bits.redirect.brTarget := target // DontCare
-  io.out.bits.redirect.taken := true.B
   io.out.bits.redirect.brTag := uop.brTag
   io.out.bits.redirect._type := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
-  io.out.bits.redirect.taken := false.B // DontCare
+  io.out.bits.redirect.taken := true.B
+  io.out.bits.redirect.hist := uop.cf.hist
+  io.out.bits.redirect.tageMeta := uop.cf.tageMeta
+  io.out.bits.redirect.fetchIdx := uop.cf.fetchOffset >> 2.U  //TODO: consider RVC
+  io.out.bits.redirect.btbVictimWay := uop.cf.btbVictimWay
+  io.out.bits.redirect.btbPredCtr := uop.cf.btbPredCtr
+  io.out.bits.redirect.btbHitWay := uop.cf.btbHitWay
+  io.out.bits.redirect.rasSp := uop.cf.rasSp
+  io.out.bits.redirect.rasTopCtr := uop.cf.rasTopCtr
   io.out.bits.redirect.isException := false.B
   io.out.bits.redirect.roqIdx := uop.roqIdx
   io.out.bits.redirect.freelistAllocPtr := uop.freelistAllocPtr

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -280,6 +280,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     debugMonitor.io.instrCnt := instrCnt
 
     // BPU temp Perf Cnt
-    BoringUtils.addSource(hitTrap, "XSTRAP_BPU")
+    if(EnableBPU){
+      BoringUtils.addSource(hitTrap, "XSTRAP_BPU")
+    }
   }
 }

src/main/scala/xiangshan/frontend/FakeICache.scala

@@ -51,7 +51,7 @@ class FakeCache extends XSModule with HasICacheConst {
 
   val memByte = 128 * 1024 * 1024
 
-  val ramHelpers = Array.fill(FetchWidth/2)(Module(new RAMHelper(memByte)).io)
+  val ramHelpers = Array.fill(FetchWidth/2 + 1)(Module(new RAMHelper(memByte)).io) 
   ramHelpers.foreach(_.clk := clock)
 
   //fake instruction fetch pipeline
@@ -61,7 +61,8 @@ class FakeCache extends XSModule with HasICacheConst {
   val s1_valid = io.in.valid
   val s2_ready = WireInit(false.B)
   val s1_fire = s1_valid && s2_ready
-  val gpc = groupPC(io.in.bits.addr)
+  //val gpc = groupPC(io.in.bits.addr)
+  val gpc = (io.in.bits.addr) //use fetch pc
   io.in.ready := s2_ready
 
   val offsetBits = log2Up(memByte)
@@ -73,8 +74,27 @@ class FakeCache extends XSModule with HasICacheConst {
   for(i <- ramHelpers.indices) {
     val rIdx = index(gpc) + i.U
     ramHelpers(i).rIdx := rIdx
-    ramOut(2*i) := ramHelpers(i).rdata.tail(32)
-    ramOut(2*i+1) := ramHelpers(i).rdata.head(32)
+    when(gpc(2) === "b0".U){
+      //little ending
+      ramOut(0) := ramHelpers(0).rdata.tail(32)
+      ramOut(1) := ramHelpers(0).rdata.head(32)
+      ramOut(2) := ramHelpers(1).rdata.tail(32)
+      ramOut(3) := ramHelpers(1).rdata.head(32)
+      ramOut(4) := ramHelpers(2).rdata.tail(32)
+      ramOut(5) := ramHelpers(2).rdata.head(32)
+      ramOut(6) := ramHelpers(3).rdata.tail(32)
+      ramOut(7) := ramHelpers(3).rdata.head(32)
+    } .otherwise {
+      ramOut(0) := ramHelpers(0).rdata.head(32)
+      ramOut(1) := ramHelpers(1).rdata.tail(32)
+      ramOut(2) := ramHelpers(1).rdata.head(32)
+      ramOut(3) := ramHelpers(2).rdata.tail(32)
+      ramOut(4) := ramHelpers(2).rdata.head(32)
+      ramOut(5) := ramHelpers(3).rdata.tail(32)
+      ramOut(6) := ramHelpers(3).rdata.head(32)
+      ramOut(7) := ramHelpers(4).rdata.tail(32)
+
+    }
     Seq(
       ramHelpers(i).wmask,
       ramHelpers(i).wdata,

src/main/scala/xiangshan/frontend/IFU.scala

-package xiangshan.frontend
+ package xiangshan.frontend
 
 import chisel3._
 import chisel3.util._
@@ -8,9 +8,9 @@ import xiangshan.utils._
 
 trait HasIFUConst { this: XSModule =>
   val resetVector = 0x80000000L//TODO: set reset vec
-  val enableBPU = false
   val groupAlign = log2Up(FetchWidth * 4)
   def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
+  def snpc(pc: UInt): UInt = pc + (1 << groupAlign).U
   
 }
 
@@ -31,8 +31,10 @@ class FakeBPU extends XSModule{
     val predecode = Flipped(ValidIO(new Predecode))
   })
 
-  io.btbOut.valid := false.B
+  io.btbOut.valid := true.B
   io.btbOut.bits <> DontCare
+  io.btbOut.bits.redirect := GTimer() === 1.U
+  io.btbOut.bits.target := "h080001234".U
   io.tageOut.valid := false.B
   io.tageOut.bits <> DontCare
 }
@@ -48,16 +50,16 @@ class IFU extends XSModule with HasIFUConst
     //-------------------------
     //local
     val if1_npc = WireInit(0.U(VAddrBits.W))
-    val if1_valid = !reset.asBool //TODO:this is ugly
+    val if1_valid = !reset.asBool 
     val if1_pc = RegInit(resetVector.U(VAddrBits.W))
     //next
     val if2_ready = WireInit(false.B)
-    val if2_snpc = Cat(if1_pc(VAddrBits-1, groupAlign) + 1.U, 0.U(groupAlign.W))
-    val if1_ready = if2_ready
+    val if2_snpc = snpc(if1_pc) //TODO: this is ugly
+    val needflush = WireInit(false.B)
 
     //pipe fire
-    val if1_fire = if1_valid && if1_ready 
-    val if1_pcUpdate = io.redirectInfo.flush() || if1_fire
+    val if1_fire = if1_valid && if2_ready 
+    val if1_pcUpdate = if1_fire || needflush
 
     when(RegNext(reset.asBool) && !reset.asBool){
     //when((GTimer() === 501.U)){ //TODO:this is ugly
@@ -99,8 +101,7 @@ class IFU extends XSModule with HasIFUConst
     if2_ready := (if2_fire) || !if2_valid
 
     io.icacheReq.valid := if2_valid
-    io.icacheReq.bits.addr := groupPC(if2_pc)
-    io.icacheReq.bits.flush := io.redirectInfo.flush()
+    io.icacheReq.bits.addr := if2_pc
 
     when(if2_valid && if2_btb_taken)
     {
@@ -108,11 +109,10 @@ class IFU extends XSModule with HasIFUConst
     }
 
     XSDebug("[IF2]if2_valid:%d  ||  if2_pc:0x%x   || if3_ready:%d                                        ",if2_valid,if2_pc,if3_ready)
-    //XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target)
     XSDebug(false,if2_fire,"------IF2->fire!!!")
     XSDebug(false,true.B,"\n")
     XSDebug("[IF2-Icache-Req] icache_in_valid:%d  icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready)
-
+    XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target)
     //-------------------------
     //      IF3  icache hit check
     //-------------------------
@@ -148,41 +148,61 @@ class IFU extends XSModule with HasIFUConst
     val if4_tage_target = bpu.io.tageOut.bits.target
     val if4_tage_taken = bpu.io.tageOut.valid && bpu.io.tageOut.bits.redirect
     val if4_tage_insMask = bpu.io.tageOut.bits.instrValid
+    val if4_btb_missPre = WireInit(false.B)
+
     XSDebug("[IF4]if4_valid:%d  ||  if4_pc:0x%x   if4_npc:0x%x\n",if4_valid,if4_pc,if4_npc)
-    //XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target)
+    XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target)
     XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d   icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready)
 
     when(if4_valid && io.icacheResp.fire() && if4_tage_taken)
     {
       if1_npc := if4_tage_target
     }
-    
+    //redirect: tage result differ btb
+    if4_btb_missPre := (if4_tage_taken ^ if4_btb_taken) || (if4_tage_taken && if4_btb_taken && (if4_tage_target =/=  if4_btb_target))
+
+    when(!if4_tage_taken && if4_btb_taken){
+      if1_npc := snpc(if4_pc)
+    }
 
     //redirect: miss predict
     when(io.redirectInfo.flush()){
       if1_npc := io.redirectInfo.redirect.target
+    }
+    XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x  \n",io.redirectInfo.redirect.target.asUInt)
+    
+  
+    //flush pipline
+    needflush := if4_btb_missPre || io.redirectInfo.flush()
+    when(needflush){
       if3_valid := false.B
       if4_valid := false.B
     }
-    XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x  \n",io.redirectInfo.redirect.target.asUInt)
+    //flush ICache
+    io.icacheReq.bits.flush := needflush
 
     //Output -> iBuffer
-    //io.fetchPacket <> DontCare
-    if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) && (GTimer() > 500.U)
-    io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush()
+    if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) //&& (GTimer() > 500.U)
+    io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush()   //if4_miss_pred should not disable out valid
     io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut
-    if(enableBPU){io.fetchPacket.bits.mask := (Fill(FetchWidth*2, 1.U(1.W)) & Reverse(Cat(if4_tage_insMask.map(i => Fill(2, i.asUInt))).asUInt)) << if4_pc(2+log2Up(FetchWidth)-1, 1)}
-    else{io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 1)}    
+    if(EnableBPU){
+      io.fetchPacket.bits.mask := Mux( if4_tage_taken,
+        Fill(FetchWidth*2, 1.U(1.W)) & Reverse(Cat(if4_tage_insMask.map(i => Fill(2, i.asUInt)))).asUInt ,
+        Fill(FetchWidth*2, 1.U(1.W))
+      )
+    }
+    else{
+      io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) //TODO : consider cross cacheline fetch
+    }    
     io.fetchPacket.bits.pc := if4_pc
 
     XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] starPC:0x%x   GroupPC:0x%xn\n",if4_pc.asUInt,groupPC(if4_pc).asUInt)
     XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instrmask %b\n",io.fetchPacket.bits.mask.asUInt)
     for(i <- 0 until FetchWidth){
-      //io.fetchPacket.bits.pnpc(i) := if1_npc
       when (if4_tage_taken && i.U === OHToUInt(HighestBit(if4_tage_insMask.asUInt, FetchWidth))) {
         io.fetchPacket.bits.pnpc(i) := if1_npc
       }.otherwise {
-        io.fetchPacket.bits.pnpc(i) := groupPC(if4_pc) + (i + 1).U << 2.U // TODO: has bug
+        io.fetchPacket.bits.pnpc(i) := if4_pc + ((i + 1).U << 2.U) //use fetch PC
       }
       XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instruction %x    pnpc:0x%x\n",io.fetchPacket.bits.instrs(i).asUInt,io.fetchPacket.bits.pnpc(i).asUInt)
     }    
@@ -197,11 +217,11 @@ class IFU extends XSModule with HasIFUConst
     //to BPU
     bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid
     bpu.io.predecode.bits <> io.icacheResp.bits.predecode
-    bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 2) //TODO: consider RVC
-
+    bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) //TODO: consider RVC && consider cross cacheline fetch
     bpu.io.redirectInfo := io.redirectInfo
-
-    io.icacheResp.ready := io.fetchPacket.ready && (GTimer() > 500.U)
+    
+    
+    io.icacheResp.ready := io.fetchPacket.ready //&& (GTimer() > 500.U)
 
 }
 

src/main/scala/xiangshan/utils/LogUtils.scala

@@ -17,27 +17,13 @@ object XSLogLevel extends Enumeration {
 }
 
 object XSLog {
-
-  def displayLog: Bool = {
-    val disp_begin, disp_end = WireInit(0.U(64.W))
-    BoringUtils.addSink(disp_begin, "DISPLAY_LOG_START")
-    BoringUtils.addSink(disp_end, "DISPLAY_LOG_END")
-    assert(disp_begin <= disp_end)
-    (GTimer() >= disp_begin) && (GTimer() <= disp_end)
-  }
-
-  def xsLogLevel: UInt = {
-    val log_level = WireInit(0.U(64.W))
-    BoringUtils.addSink(log_level, "DISPLAY_LOG_LEVEL")
-    assert(log_level < XSLogLevel.maxId.U)
-    log_level
-  }
-
   def apply(debugLevel: XSLogLevel)
            (prefix: Boolean, cond: Bool, pable: Printable)
            (implicit name: String): Any = {
     val commonInfo = p"[$debugLevel][time=${GTimer()}] $name: "
-    when (debugLevel.id.U >= xsLogLevel && cond && displayLog) {
+    val logEnable = WireInit(false.B)
+    BoringUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE")
+    when (cond && logEnable) {
       printf((if (prefix) commonInfo else p"") + pable)
     }
   }

src/test/csrc/common.h

@@ -42,18 +42,6 @@ void init_device(void);
 bool is_finished(void);
 int get_exit_code(void);
 
-// log
-enum {
-  LOG_ALL = 0,
-  LOG_DEBUG,
-  LOG_INFO,
-  LOG_WARN,
-  LOG_ERROR,
-  LOG_OFF
-};
-
-uint64_t getLogLevel(const char * str);
-
 void app_error(const char *fmt, ...);
 
 int monitor(void);

src/test/csrc/emu.h

@@ -26,7 +26,7 @@ class Emulator {
   // emu control variable
   uint32_t seed;
   uint64_t max_cycles, cycles;
-  uint64_t log_begin, log_end, log_level;
+  uint64_t log_begin, log_end;
 
   std::vector<const char *> parse_args(int argc, const char *argv[]);
 
@@ -71,7 +71,7 @@ class Emulator {
     image(nullptr),
     dut_ptr(new std::remove_reference<decltype(*dut_ptr)>::type),
     seed(0), max_cycles(-1), cycles(0),
-    log_begin(0), log_end(-1), log_level(LOG_ALL)
+    log_begin(0), log_end(-1)
   {
     // init emu
     auto args = parse_args(argc, argv);
@@ -84,7 +84,6 @@ class Emulator {
     // set log time range and log level
     dut_ptr->io_logCtrl_log_begin = log_begin;
     dut_ptr->io_logCtrl_log_end = log_end;
-    dut_ptr->io_logCtrl_log_level = log_level;
 
     // init ram
     extern void init_ram(const char *img);

src/test/csrc/log.cpp

-#include <cstdio>
-#include <cstring>
-#include "common.h"
-
-uint64_t getLogLevel(const char * str) {
-  if(!strcmp("ALL", str)){
-    return LOG_ALL;
-  } else if(!strcmp("DEBUG", str)){
-    return LOG_DEBUG;
-  } else if(!strcmp("INFO", str)){
-    return LOG_INFO;
-  } else if(!strcmp("WARN", str)){
-    return LOG_WARN;
-  } else if(!strcmp("ERROR", str)){
-    return LOG_ERROR;
-  } else if(!strcmp("OFF", str)){
-    return LOG_OFF;
-  } else {
-    printf("Unknown verbosity level!\n");
-    exit(-1);
-  }
-}

src/test/csrc/main.cpp

@@ -22,7 +22,6 @@ const struct option Emulator::long_options[] = {
   { "image",          1, NULL, 'i' },
   { "log-begin",      1, NULL, 'b' },
   { "log-end",        1, NULL, 'e' },
-  { "verbose",        1, NULL, 'v' },
   { "help",           0, NULL, 'h' },
   { 0,                0, NULL,  0  }
 };
@@ -35,7 +34,6 @@ void Emulator::print_help(const char *file) {
   printf("  -i, --image=FILE      run with this image file\n");
   printf("  -b, --log-begin=NUM   display log from NUM th cycle\n");
   printf("  -e, --log-end=NUM     stop display log at NUM th cycle\n");
-  printf("  -v, --verbose=STR     verbosity level, can be one of [ALL, DEBUG, INFO, WARN, ERROR]\n");
   printf("  -h, --help            print program help info\n");
   printf("\n");
 }
@@ -43,7 +41,7 @@ void Emulator::print_help(const char *file) {
 std::vector<const char *> Emulator::parse_args(int argc, const char *argv[]) {
   std::vector<const char *> args = { argv[0] };
   int o;
-  while ( (o = getopt_long(argc, const_cast<char *const*>(argv), "-s:C:hi:m:b:e:v:", long_options, NULL)) != -1) {
+  while ( (o = getopt_long(argc, const_cast<char *const*>(argv), "-s:C:hi:m:b:e:", long_options, NULL)) != -1) {
     switch (o) {
       case 's': 
         if(std::string(optarg) != "NO_SEED") {
@@ -58,7 +56,6 @@ std::vector<const char *> Emulator::parse_args(int argc, const char *argv[]) {
                 break;
       case 'b': log_begin = atoll(optarg);  break;
       case 'e': log_end = atoll(optarg); break;
-      case 'v': log_level = getLogLevel(optarg); break;
       default:
                 print_help(argv[0]);
                 exit(0);

src/test/scala/top/XSSim.scala

@@ -8,6 +8,7 @@ import bus.axi4._
 import chisel3.stage.ChiselGeneratorAnnotation
 import device.AXI4RAM
 import xiangshan._
+import utils._
 
 class DiffTestIO extends XSBundle {
   val r = Output(Vec(64, UInt(XLEN.W)))
@@ -81,14 +82,8 @@ class XSSimTop extends Module {
   BoringUtils.addSink(difftest.scause, "difftestScause")
   io.difftest := difftest
 
-  val log_begin, log_end, log_level = Wire(UInt(64.W))
-  log_begin := io.logCtrl.log_begin
-  log_end := io.logCtrl.log_end
-  log_level := io.logCtrl.log_level
-
-  BoringUtils.addSource(log_begin, "DISPLAY_LOG_START")
-  BoringUtils.addSource(log_end, "DISPLAY_LOG_END")
-  BoringUtils.addSource(log_level, "DISPLAY_LOG_LEVEL")
+  val logEnable = (GTimer() >= io.logCtrl.log_begin) && (GTimer() < io.logCtrl.log_end)
+  BoringUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
 }
 
 object TestMain extends App {