fix stu feedback slow logic (#2252)

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -151,25 +151,13 @@ class StoreUnit(implicit p: Parameters) extends XSModule {
   io.stld_nuke_query.bits.paddr  := s1_paddr
   io.stld_nuke_query.bits.mask   := s1_in.mask
 
-  // Send TLB feedback to store issue queue
-  // Store feedback is generated in store_s1, sent to RS in store_s2
-  io.feedback_slow.valid           := s1_fire
-  io.feedback_slow.bits.hit        := !s1_tlb_miss
-  io.feedback_slow.bits.flushState := io.tlb.resp.bits.ptwBack
-  io.feedback_slow.bits.rsIdx      := s1_in.rsIdx
-  io.feedback_slow.bits.sourceType := RSFeedbackType.tlbMiss
-  XSDebug(io.feedback_slow.valid,
-    "S1 Store: tlbHit: %d robIdx: %d\n",
-    io.feedback_slow.bits.hit,
-    io.feedback_slow.bits.rsIdx
-  )
-  io.feedback_slow.bits.dataInvalidSqIdx := DontCare
-
   // issue
   io.issue.valid := s1_valid && !s1_tlb_miss
   io.issue.bits  := RegEnable(s0_in, s0_valid)
 
-  // rs feedback
+
+  // Send TLB feedback to store issue queue
+  // Store feedback is generated in store_s1, sent to RS in store_s2
   val s1_feedback = Wire(Valid(new RSFeedback))
   s1_feedback.valid                 := s1_valid & !s1_in.isHWPrefetch
   s1_feedback.bits.hit              := !s1_tlb_miss
@@ -183,6 +171,8 @@ class StoreUnit(implicit p: Parameters) extends XSModule {
     s1_feedback.bits.rsIdx
   )
 
+  io.feedback_slow := s1_feedback
+
   // get paddr from dtlb, check if rollback is needed
   // writeback store inst to lsq
   s1_out        := s1_in