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87305886
编写于
5月 24, 2019
作者:
Z
Zihao Yu
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
noop,ISU: add forwarding
上级
c8ad3f2c
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
39 addition
and
8 deletion
+39
-8
src/main/scala/noop/Bundle.scala
src/main/scala/noop/Bundle.scala
+8
-0
src/main/scala/noop/EXU.scala
src/main/scala/noop/EXU.scala
+9
-2
src/main/scala/noop/IDU.scala
src/main/scala/noop/IDU.scala
+2
-0
src/main/scala/noop/ISU.scala
src/main/scala/noop/ISU.scala
+16
-5
src/main/scala/noop/NOOP.scala
src/main/scala/noop/NOOP.scala
+3
-0
src/main/scala/noop/WBU.scala
src/main/scala/noop/WBU.scala
+1
-1
未找到文件。
src/main/scala/noop/Bundle.scala
浏览文件 @
87305886
...
@@ -15,6 +15,8 @@ class CtrlPathIO extends Bundle
...
@@ -15,6 +15,8 @@ class CtrlPathIO extends Bundle
val
rfDest
=
Output
(
UInt
(
5.
W
))
val
rfDest
=
Output
(
UInt
(
5.
W
))
val
isInvOpcode
=
Output
(
Bool
())
val
isInvOpcode
=
Output
(
Bool
())
val
isNoopTrap
=
Output
(
Bool
())
val
isNoopTrap
=
Output
(
Bool
())
val
isSrc1Forward
=
Output
(
Bool
())
val
isSrc2Forward
=
Output
(
Bool
())
}
}
class
DataPathIO
extends
Bundle
{
class
DataPathIO
extends
Bundle
{
...
@@ -54,3 +56,9 @@ class FunctionUnitIO extends Bundle with HasDecodeConst {
...
@@ -54,3 +56,9 @@ class FunctionUnitIO extends Bundle with HasDecodeConst {
}))
}))
val
out
=
Decoupled
(
Output
(
UInt
(
32.
W
)))
val
out
=
Decoupled
(
Output
(
UInt
(
32.
W
)))
}
}
class
ForwardIO
extends
Bundle
{
val
rfWen
=
Output
(
Bool
())
val
rfDest
=
Output
(
UInt
(
5.
W
))
val
fire
=
Output
(
Bool
())
}
src/main/scala/noop/EXU.scala
浏览文件 @
87305886
...
@@ -12,6 +12,8 @@ class EXU extends Module with HasFuType {
...
@@ -12,6 +12,8 @@ class EXU extends Module with HasFuType {
val
out
=
Decoupled
((
new
PcCtrlDataIO
))
val
out
=
Decoupled
((
new
PcCtrlDataIO
))
val
br
=
new
BranchIO
val
br
=
new
BranchIO
val
dmem
=
new
SimpleBus
val
dmem
=
new
SimpleBus
val
forward
=
new
ForwardIO
val
wbData
=
Input
(
UInt
(
32.
W
))
val
csr
=
new
Bundle
{
val
csr
=
new
Bundle
{
val
isCsr
=
Output
(
Bool
())
val
isCsr
=
Output
(
Bool
())
val
in
=
Flipped
(
Decoupled
(
UInt
(
32.
W
)))
val
in
=
Flipped
(
Decoupled
(
UInt
(
32.
W
)))
...
@@ -20,8 +22,9 @@ class EXU extends Module with HasFuType {
...
@@ -20,8 +22,9 @@ class EXU extends Module with HasFuType {
}
}
})
})
val
(
src1
,
src2
,
fuType
,
fuOpType
)
=
(
io
.
in
.
bits
.
data
.
src1
,
io
.
in
.
bits
.
data
.
src2
,
val
src1
=
Mux
(
io
.
in
.
bits
.
ctrl
.
isSrc1Forward
,
io
.
wbData
,
io
.
in
.
bits
.
data
.
src1
)
io
.
in
.
bits
.
ctrl
.
fuType
,
io
.
in
.
bits
.
ctrl
.
fuOpType
)
val
src2
=
Mux
(
io
.
in
.
bits
.
ctrl
.
isSrc2Forward
,
io
.
wbData
,
io
.
in
.
bits
.
data
.
src2
)
val
(
fuType
,
fuOpType
)
=
(
io
.
in
.
bits
.
ctrl
.
fuType
,
io
.
in
.
bits
.
ctrl
.
fuOpType
)
val
fuValids
=
Wire
(
Vec
(
FuTypeNum
,
Bool
()))
val
fuValids
=
Wire
(
Vec
(
FuTypeNum
,
Bool
()))
(
0
until
FuTypeNum
).
map
(
i
=>
fuValids
(
i
)
:=
(
fuType
===
i
.
U
)
&&
io
.
in
.
valid
)
(
0
until
FuTypeNum
).
map
(
i
=>
fuValids
(
i
)
:=
(
fuType
===
i
.
U
)
&&
io
.
in
.
valid
)
...
@@ -74,6 +77,10 @@ class EXU extends Module with HasFuType {
...
@@ -74,6 +77,10 @@ class EXU extends Module with HasFuType {
io
.
in
.
ready
:=
!
io
.
in
.
valid
||
io
.
out
.
fire
()
io
.
in
.
ready
:=
!
io
.
in
.
valid
||
io
.
out
.
fire
()
io
.
forward
.
fire
:=
io
.
out
.
fire
()
io
.
forward
.
rfWen
:=
io
.
in
.
bits
.
ctrl
.
rfWen
io
.
forward
.
rfDest
:=
io
.
in
.
bits
.
ctrl
.
rfDest
// perfcnt
// perfcnt
io
.
csr
.
instrType
(
FuAlu
)
:=
alu
.
io
.
out
.
fire
()
io
.
csr
.
instrType
(
FuAlu
)
:=
alu
.
io
.
out
.
fire
()
io
.
csr
.
instrType
(
FuBru
)
:=
bru
.
io
.
out
.
fire
()
io
.
csr
.
instrType
(
FuBru
)
:=
bru
.
io
.
out
.
fire
()
...
...
src/main/scala/noop/IDU.scala
浏览文件 @
87305886
...
@@ -15,6 +15,8 @@ class IDU extends Module with HasDecodeConst {
...
@@ -15,6 +15,8 @@ class IDU extends Module with HasDecodeConst {
val
instrType
::
fuType
::
fuOpType
::
Nil
=
val
instrType
::
fuType
::
fuOpType
::
Nil
=
ListLookup
(
instr
,
Instructions
.
DecodeDefault
,
Instructions
.
DecodeTable
)
ListLookup
(
instr
,
Instructions
.
DecodeDefault
,
Instructions
.
DecodeTable
)
io
.
out
.
bits
:=
DontCare
io
.
out
.
bits
.
ctrl
.
fuType
:=
fuType
io
.
out
.
bits
.
ctrl
.
fuType
:=
fuType
io
.
out
.
bits
.
ctrl
.
fuOpType
:=
fuOpType
io
.
out
.
bits
.
ctrl
.
fuOpType
:=
fuOpType
...
...
src/main/scala/noop/ISU.scala
浏览文件 @
87305886
...
@@ -24,6 +24,7 @@ class ISU extends Module with HasSrcType {
...
@@ -24,6 +24,7 @@ class ISU extends Module with HasSrcType {
val
out
=
Decoupled
(
new
PcCtrlDataIO
)
val
out
=
Decoupled
(
new
PcCtrlDataIO
)
val
wb
=
Flipped
(
new
WriteBackIO
)
val
wb
=
Flipped
(
new
WriteBackIO
)
val
flush
=
Input
(
Bool
())
val
flush
=
Input
(
Bool
())
val
forward
=
Flipped
(
new
ForwardIO
)
val
difftestRegs
=
Output
(
Vec
(
32
,
UInt
(
32.
W
)))
val
difftestRegs
=
Output
(
Vec
(
32
,
UInt
(
32.
W
)))
val
rawStall
=
Output
(
Bool
())
val
rawStall
=
Output
(
Bool
())
val
exuBusy
=
Output
(
Bool
())
val
exuBusy
=
Output
(
Bool
())
...
@@ -34,9 +35,20 @@ class ISU extends Module with HasSrcType {
...
@@ -34,9 +35,20 @@ class ISU extends Module with HasSrcType {
val
rfSrc2
=
Mux
(
io
.
in
.
bits
.
ctrl
.
src2Type
===
Src2Reg
,
io
.
in
.
bits
.
ctrl
.
rfSrc2
,
0.
U
)
val
rfSrc2
=
Mux
(
io
.
in
.
bits
.
ctrl
.
src2Type
===
Src2Reg
,
io
.
in
.
bits
.
ctrl
.
rfSrc2
,
0.
U
)
val
rfDest
=
Mux
(
io
.
in
.
bits
.
ctrl
.
rfWen
,
io
.
in
.
bits
.
ctrl
.
rfDest
,
0.
U
)
val
rfDest
=
Mux
(
io
.
in
.
bits
.
ctrl
.
rfWen
,
io
.
in
.
bits
.
ctrl
.
rfDest
,
0.
U
)
val
src1ForwardNextCycle
=
(
rfSrc1
=/=
0.
U
)
&&
(
rfSrc1
===
io
.
forward
.
rfDest
)
&&
io
.
forward
.
rfWen
&&
io
.
forward
.
fire
val
src2ForwardNextCycle
=
(
rfSrc2
=/=
0.
U
)
&&
(
rfSrc2
===
io
.
forward
.
rfDest
)
&&
io
.
forward
.
rfWen
&&
io
.
forward
.
fire
val
src1Forward
=
(
rfSrc1
=/=
0.
U
)
&&
(
rfSrc1
===
io
.
wb
.
rfDest
)
&&
io
.
wb
.
rfWen
&&
!
src1ForwardNextCycle
val
src2Forward
=
(
rfSrc2
=/=
0.
U
)
&&
(
rfSrc2
===
io
.
wb
.
rfDest
)
&&
io
.
wb
.
rfWen
&&
!
src2ForwardNextCycle
val
sb
=
new
ScoreBoard
val
src1Ready
=
!
sb
.
isBusy
(
rfSrc1
)
||
src1ForwardNextCycle
||
src1Forward
val
src2Ready
=
!
sb
.
isBusy
(
rfSrc2
)
||
src2ForwardNextCycle
||
src2Forward
io
.
out
.
valid
:=
io
.
in
.
valid
&&
src1Ready
&&
src2Ready
&&
!
io
.
flush
val
rf
=
new
RegFile
val
rf
=
new
RegFile
val
rs1Data
=
rf
.
read
(
rfSrc1
)
val
rs1Data
=
Mux
(
src1Forward
,
io
.
wb
.
rfWdata
,
rf
.
read
(
rfSrc1
)
)
val
rs2Data
=
rf
.
read
(
rfSrc2
)
val
rs2Data
=
Mux
(
src2Forward
,
io
.
wb
.
rfWdata
,
rf
.
read
(
rfSrc2
)
)
io
.
out
.
bits
.
data
.
src1
:=
Mux
(
io
.
in
.
bits
.
ctrl
.
src1Type
===
Src1Pc
,
io
.
in
.
bits
.
pc
,
rs1Data
)
io
.
out
.
bits
.
data
.
src1
:=
Mux
(
io
.
in
.
bits
.
ctrl
.
src1Type
===
Src1Pc
,
io
.
in
.
bits
.
pc
,
rs1Data
)
io
.
out
.
bits
.
data
.
src2
:=
Mux
(
io
.
in
.
bits
.
ctrl
.
src2Type
===
Src2Reg
,
rs2Data
,
io
.
in
.
bits
.
data
.
imm
)
io
.
out
.
bits
.
data
.
src2
:=
Mux
(
io
.
in
.
bits
.
ctrl
.
src2Type
===
Src2Reg
,
rs2Data
,
io
.
in
.
bits
.
data
.
imm
)
io
.
out
.
bits
.
data
.
imm
:=
io
.
in
.
bits
.
data
.
imm
io
.
out
.
bits
.
data
.
imm
:=
io
.
in
.
bits
.
data
.
imm
...
@@ -52,9 +64,8 @@ class ISU extends Module with HasSrcType {
...
@@ -52,9 +64,8 @@ class ISU extends Module with HasSrcType {
o
.
isNoopTrap
:=
i
.
isNoopTrap
o
.
isNoopTrap
:=
i
.
isNoopTrap
}
}
io
.
out
.
bits
.
pc
:=
io
.
in
.
bits
.
pc
io
.
out
.
bits
.
pc
:=
io
.
in
.
bits
.
pc
io
.
out
.
bits
.
ctrl
.
isSrc1Forward
:=
src1ForwardNextCycle
val
sb
=
new
ScoreBoard
io
.
out
.
bits
.
ctrl
.
isSrc2Forward
:=
src2ForwardNextCycle
io
.
out
.
valid
:=
io
.
in
.
valid
&&
!
sb
.
isBusy
(
rfSrc1
)
&&
!
sb
.
isBusy
(
rfSrc2
)
&&
!
io
.
flush
when
(
io
.
wb
.
rfWen
)
{
when
(
io
.
wb
.
rfWen
)
{
rf
.
write
(
io
.
wb
.
rfDest
,
io
.
wb
.
rfWdata
)
rf
.
write
(
io
.
wb
.
rfDest
,
io
.
wb
.
rfWdata
)
...
...
src/main/scala/noop/NOOP.scala
浏览文件 @
87305886
...
@@ -91,6 +91,9 @@ class NOOP extends Module with NOOPConfig with HasCSRConst with HasFuType {
...
@@ -91,6 +91,9 @@ class NOOP extends Module with NOOPConfig with HasCSRConst with HasFuType {
wbu
.
io
.
brIn
<>
exu
.
io
.
br
wbu
.
io
.
brIn
<>
exu
.
io
.
br
isu
.
io
.
wb
<>
wbu
.
io
.
wb
isu
.
io
.
wb
<>
wbu
.
io
.
wb
ifu
.
io
.
br
<>
wbu
.
io
.
brOut
ifu
.
io
.
br
<>
wbu
.
io
.
brOut
// forward
isu
.
io
.
forward
<>
exu
.
io
.
forward
exu
.
io
.
wbData
:=
wbu
.
io
.
wb
.
rfWdata
val
xbar
=
Module
(
new
SimpleBusCrossbar
(
1
,
AddressSpace
))
val
xbar
=
Module
(
new
SimpleBusCrossbar
(
1
,
AddressSpace
))
val
dmem
=
xbar
.
io
.
out
(
0
)
val
dmem
=
xbar
.
io
.
out
(
0
)
...
...
src/main/scala/noop/WBU.scala
浏览文件 @
87305886
...
@@ -14,7 +14,7 @@ class WBU extends Module {
...
@@ -14,7 +14,7 @@ class WBU extends Module {
io
.
wb
.
rfWen
:=
io
.
in
.
bits
.
ctrl
.
rfWen
&&
io
.
in
.
valid
io
.
wb
.
rfWen
:=
io
.
in
.
bits
.
ctrl
.
rfWen
&&
io
.
in
.
valid
io
.
wb
.
rfDest
:=
io
.
in
.
bits
.
ctrl
.
rfDest
io
.
wb
.
rfDest
:=
io
.
in
.
bits
.
ctrl
.
rfDest
io
.
wb
.
rfWdata
:=
io
.
in
.
bits
.
data
.
dest
io
.
wb
.
rfWdata
:=
Mux
(
io
.
in
.
fire
(),
io
.
in
.
bits
.
data
.
dest
,
RegEnable
(
io
.
in
.
bits
.
data
.
dest
,
io
.
in
.
fire
()))
io
.
in
.
ready
:=
true
.
B
io
.
in
.
ready
:=
true
.
B
io
.
brOut
<>
io
.
brIn
io
.
brOut
<>
io
.
brIn
...
...
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