core: pass sum

src/main/scala/core/Decode.scala

@@ -33,7 +33,7 @@ object Decode {
     InstrI -> (Src1Reg, Src2Imm),
     InstrR -> (Src1Reg, Src2Reg),
     InstrS -> (Src1Reg, Src2Imm),
-    InstrB -> (Src1Reg, Src2Reg),
+    InstrB -> (Src1Reg, Src2Imm),
     InstrU -> (Src1Pc , Src2Imm),
     InstrJ -> (Src1Pc , Src2Imm),
     InstrN -> (Src1Pc , Src2Imm)
@@ -48,7 +48,7 @@ object Decode {
   val FuTypeWidth = log2Up(FuTypeNum).W
 
   /* ALU operation type */
-  private val FuOpTypeAluNum  = 10
+  private val FuOpTypeAluNum  = 11
   val AluAdd  = "b0000".U
   val AluSll  = "b0001".U
   val AluSlt  = "b0010".U
@@ -59,14 +59,18 @@ object Decode {
   val AluAnd  = "b0111".U
   val AluSub  = "b1000".U
   val AluSar  = "b1101".U
+  val AluLui  = "b1111".U
 
   /* BRU operation type */
   private val FuOpTypeBruNum  = 10
   val BruJal  = "b1000".U
   val BruJalr = "b1001".U
+  val BruBeq  = "b0000".U
+  val BruBne  = "b0001".U
 
   /* LSU operation type */
   private val FuOpTypeLsuNum  = 10
+  val LsuLw   = "b0010".U
   val LsuSw   = "b1010".U
 
   /* MDU operation type */
@@ -79,12 +83,20 @@ object Decode {
 
   /* instruction pattern */
   val ADDI    = BitPat("b????????????_?????_000_?????_0010011")
+  val SLTIU   = BitPat("b????????????_?????_011_?????_0010011")
+
+  val ADD     = BitPat("b0000000_?????_?????_000_?????_0110011")
 
   val AUIPC   = BitPat("b????????????????????_?????_0010111")
+  val LUI     = BitPat("b????????????????????_?????_0110111")
 
   val JAL     = BitPat("b????????????????????_?????_1101111")
   val JALR    = BitPat("b????????????_?????_000_?????_1100111")
 
+  val BNE     = BitPat("b???????_?????_?????_001_?????_1100011")
+  val BEQ     = BitPat("b???????_?????_?????_000_?????_1100011")
+
+  val LW      = BitPat("b????????????_?????_010_?????_0000011")
   val SW      = BitPat("b???????_?????_?????_010_?????_0100011")
 
   val TRAP    = BitPat("b????????????_?????_000_?????_1101011")
@@ -96,12 +108,20 @@ object Decode {
     /*                     Instr |  FU  | FU OP |
      *                     Type  | Type |  Type | */
     ADDI           -> List(InstrI, FuAlu, AluAdd),
+    SLTIU          -> List(InstrI, FuAlu, AluSltu),
+
+    ADD            -> List(InstrR, FuAlu, AluAdd),
 
     AUIPC          -> List(InstrU, FuAlu, AluAdd),
+    LUI            -> List(InstrU, FuAlu, AluLui),
 
     JAL            -> List(InstrJ, FuBru, BruJal),
     JALR           -> List(InstrI, FuBru, BruJalr),
 
+    BEQ            -> List(InstrB, FuBru, BruBeq),
+    BNE            -> List(InstrB, FuBru, BruBne),
+
+    LW             -> List(InstrI, FuLsu, LsuLw),
     SW             -> List(InstrS, FuLsu, LsuSw),
 
     TRAP           -> List(InstrI, FuAlu, AluAdd)

src/main/scala/core/EXU.scala

@@ -6,12 +6,16 @@ import chisel3.util._
 import Decode._
 
 object LookupTree {
+  private val useMuxTree = true
+
   def apply[T <: Data](key: UInt, mapping: Iterable[(UInt, T)]): T =
     Mux1H(mapping.map(p => (p._1 === key, p._2)))
+
+  def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
+    if (useMuxTree) apply(key, mapping) else MuxLookup(key, default, mapping.toSeq)
 }
 
 class ALU {
-  private val useMuxTree = true
   def access(src1: UInt, src2: UInt, func: UInt): UInt = {
     val shamt = src2(4, 0)
     val funcList = List(
@@ -24,25 +28,26 @@ class ALU {
       AluOr   -> (src1  |  src2),
       AluAnd  -> (src1  &  src2),
       AluSub  -> (src1  -  src2),
+      AluLui  -> src2,
       AluSar  -> ((src1.asSInt >> shamt).asUInt)
     )
 
-    if (useMuxTree) LookupTree(func, funcList)
-    else MuxLookup(func, 0.U, funcList)
+    LookupTree(func, 0.U, funcList)
   }
 }
 
 class BRU {
   private val useMuxTree = true
-  def access(src1: UInt, src2: UInt, func: UInt): (UInt, Bool) = {
+  def access(pc: UInt, offset: UInt, src1: UInt, src2: UInt, func: UInt): (UInt, Bool) = {
     val funcList = List(
-      BruJal  -> (src1  +  src2),
-      BruJalr -> (src1  +  src2)
+      BruBeq  -> (src1 === src2),
+      BruBne  -> (src1 =/= src2),
+      BruJal  -> true.B,
+      BruJalr -> true.B
     )
 
-    val target = (if (useMuxTree) LookupTree(func, funcList)
-                  else MuxLookup(func, 0.U, funcList))
-    val isTaken = func(3)
+    val target = Mux(func === BruJalr, src1 + src2, pc + offset)
+    val isTaken = LookupTree(func, false.B, funcList)
     (target, isTaken)
   }
 }
@@ -54,8 +59,7 @@ class LSU {
       LsuSw   -> (src1  +  src2)
     )
 
-    val addr = (if (useMuxTree) LookupTree(func, funcList)
-                else MuxLookup(func, 0.U, funcList))
+    val addr = LookupTree(func, 0.U, funcList)
     val wen = func(3)
     (addr, wen)
   }
@@ -72,7 +76,8 @@ class EXU extends Module {
   val (src1, src2, fuType, fuOpType) = (io.in.data.src1, io.in.data.src2, io.in.ctrl.fuType, io.in.ctrl.fuOpType)
   val aluOut = (new ALU).access(src1 = src1, src2 = src2, func = fuOpType)
 
-  val (bruOut, bruIsTaken) = (new BRU).access(src1 = src1, src2 = src2, func = fuOpType)
+  val (bruOut, bruIsTaken) = (new BRU).access(pc = io.in.pc, offset = src2,
+    src1 = src1, src2 = io.in.data.dest, func = fuOpType)
   io.br.isTaken := (fuType === FuBru) && bruIsTaken
   io.br.target := bruOut
 
@@ -93,4 +98,6 @@ class EXU extends Module {
     o.rfDest := i.rfDest
   }
   io.out.pc := io.in.pc
+
+  printf("EXU: src1 = 0x%x, src2 = 0x%x\n", src1, src2)
 }

src/main/scala/core/IDU.scala

@@ -27,7 +27,7 @@ class IDU extends Module {
   io.out.data.src2 := LookupTree(instrType, List(
     InstrI -> Cat(Fill(20, instr(31)), instr(31, 20)),
     InstrS -> Cat(Fill(20, instr(31)), instr(31, 25), instr(11, 7)),
-    InstrB -> Cat(Fill(20, instr(31)), instr(7), instr(30, 25), instr(11, 6), 0.U(1.W)),
+    InstrB -> Cat(Fill(20, instr(31)), instr(7), instr(30, 25), instr(11, 8), 0.U(1.W)),
     InstrU -> Cat(instr(31, 12), 0.U(12.W)),
     InstrJ -> Cat(Fill(12, instr(31)), instr(19, 12), instr(20), instr(30, 21), 0.U(1.W))
   ))
@@ -37,5 +37,5 @@ class IDU extends Module {
 
   io.out.ctrl.isTrap := Cat(instrType === InstrN, instr === TRAP)
 
-  printf("IDU: pc = 0x%x, instr = 0x%x, src1 = 0x%x, src2 = 0x%x\n", io.in.pc, instr, io.out.data.src1, io.out.data.src2)
+  printf("IDU: pc = 0x%x, instr = 0x%x\n", io.in.pc, instr)
 }

src/test/scala/core/NOOPTester.scala

@@ -39,8 +39,9 @@ class NOOPTester(noop: NOOP, imgPath: String) extends PeekPokeTester(noop)
     poke(noop.io.imem.in.rdata, instr)
 
     val addr = peek(noop.io.dmem.out.bits.addr).toInt
-    assert((addr & 0x3) == 0)
-    poke(noop.io.dmem.in.rdata, mem(addr >> 2))
+    val valid = peek(noop.io.dmem.out.valid)
+    assert((valid != 1) || (addr & 0x3) == 0)
+    poke(noop.io.dmem.in.rdata, if (valid == 1) mem(addr >> 2) else 0)
     val wen = peek(noop.io.dmem.out.bits.wen)
     val wdata = peek(noop.io.dmem.out.bits.wdata).toInt
     if (wen == 1) { mem(addr >> 2) = wdata }