csr,reservation_station: fix compile bug

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -818,8 +818,6 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
     "PtwReqCnt"   -> (0xb23, "perfCntPtwReqCnt"       ),
     "PtwCycleCnt" -> (0xb24, "perfCntPtwCycleCnt"     ),
     "PtwL2TlbHit" -> (0xb25, "perfCntPtwL2TlbHit"     ),
-    "CacheLoadMiss0" -> (0xb26, "perfCntCacheLoadMiss0"  ),
-    "CacheLoadMiss1" -> (0xb27, "perfCntCacheLoadMiss1"  ),
     "ITlbReqCnt0" -> (0xb28, "perfCntItlbReqCnt0"     ),
     "ITlbMissCnt0"-> (0xb29, "perfCntItlbMissCnt0"    ),
     "PtwReqCnt"   -> (0xb2a, "perfCntPtwReqCnt"       ),

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -149,7 +149,6 @@ class ReservationStation
   val tailAdd = tailAll + 1.U
   val tailSub = tailAll - 1.U
   tailAll := Mux(tailKeep, tailAll, Mux(tailInc, tailAdd, tailSub))
-  assert(tailAll < 9.U)
   // Select to Dequeue
   val deqSel = if (fifo) 0.U else PriorityEncoder(idValidQue & srcIdRdy) //may not need idx, just need oneHot, idx by IdQue's idx
   val deqSelIq = idQue(deqSel)
@@ -250,7 +249,6 @@ class ReservationStation
   ) // Note: direct by IQue's idx, different from deqSel
 
   io.numExist := Mux(tailAll === iqSize.U, (iqSize-1).U, tailAll)
-  assert(tailAll < 9.U)
 
   //-----------------------------------------
   // Issue with No Delay
@@ -439,4 +437,4 @@ class ReservationStation
   }
 
   XSPerf("utilization", tailAll)
-}
\ No newline at end of file
+}