ifu, bundle: try to simplify logic to meet timing constraints

src/main/scala/xiangshan/Bundle.scala

@@ -82,15 +82,12 @@ class BranchPrediction extends XSBundle with HasIFUConst {
   val firstBankHasHalfRVI = Bool()
   val lastBankHasHalfRVI = Bool()
 
-  def lastHalfRVIMask = Mux(firstBankHasHalfRVI, UIntToOH((bankWidth-1).U),
-                          Mux(lastBankHasHalfRVI, UIntToOH((PredictWidth-1).U),
-                            0.U(PredictWidth.W)
-                          )
-                        )
+  // assumes that only one of the two conditions could be true
+  def lastHalfRVIMask = Cat(lastBankHasHalfRVI.asUInt, 0.U(7.W), firstBankHasHalfRVI.asUInt, 0.U(7.W))
 
   def lastHalfRVIClearMask = ~lastHalfRVIMask
   // is taken from half RVI
-  def lastHalfRVITaken = ParallelORR(takens & lastHalfRVIMask)
+  def lastHalfRVITaken = (takens(bankWidth-1) && firstBankHasHalfRVI) || (takens(PredictWidth-1) && lastBankHasHalfRVI)
 
   def lastHalfRVIIdx = Mux(firstBankHasHalfRVI, (bankWidth-1).U, (PredictWidth-1).U)
   // should not be used if not lastHalfRVITaken
@@ -100,13 +97,14 @@ class BranchPrediction extends XSBundle with HasIFUConst {
   def realBrMask  = brMask  & lastHalfRVIClearMask
   def realJalMask = jalMask & lastHalfRVIClearMask
 
-  def brNotTakens = ~realTakens & realBrMask
+  def brNotTakens = ~takens & realBrMask
   def sawNotTakenBr = VecInit((0 until PredictWidth).map(i =>
                        (if (i == 0) false.B else ParallelORR(brNotTakens(i-1,0)))))
   // def hasNotTakenBrs = (brNotTakens & LowerMaskFromLowest(realTakens)).orR
   def unmaskedJmpIdx = ParallelPriorityEncoder(takens)
-  def saveHalfRVI = (firstBankHasHalfRVI && (unmaskedJmpIdx === (bankWidth-1).U || !(ParallelORR(takens)))) ||
-  (lastBankHasHalfRVI  &&  unmaskedJmpIdx === (PredictWidth-1).U)
+  // if not taken before the half RVI inst
+  def saveHalfRVI = (firstBankHasHalfRVI && !(ParallelORR(takens(bankWidth-2,0)))) ||
+  (lastBankHasHalfRVI && !(ParallelORR(takens(PredictWidth-2,0))))
   // could get PredictWidth-1 when only the first bank is valid
   def jmpIdx = ParallelPriorityEncoder(realTakens)
   // only used when taken

src/main/scala/xiangshan/frontend/IFU.scala

@@ -461,10 +461,13 @@ class IFU extends XSModule with HasIFUConst
 
   loopBufPar.noTakenMask := if4_pd.mask
   fetchPacketWire.pc := if4_pd.pc
-  (0 until PredictWidth).foreach(i => fetchPacketWire.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U))
-  when (if4_bp.taken) {
-    fetchPacketWire.pnpc(if4_bp.jmpIdx) := if4_bp.target
-  }
+  (0 until PredictWidth).foreach(i => 
+    fetchPacketWire.pnpc(i) := Mux(if4_bp.taken && if4_bp.jmpIdx === i.U,
+                                    if4_bp.target,
+                                    Mux(if4_pendingPrevHalfInstr,
+                                      (if (i == 0) Cat(bankAligned(if4_pd.pc(1))(VAddrBits-1, bankBytes), 2.U(bankBytes.W))
+                                      else Cat(bankAligned(if4_pd.pc(1))(VAddrBits-1, bankBytes), (i << 1).U(bankBytes.W) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U))),
+                                      Cat(bankAligned(if4_pd.pc(0))(VAddrBits-1, bankBytes), (i << 1).U(bankBytes.W) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)))))
   fetchPacketWire.brInfo := bpu.io.branchInfo
   (0 until PredictWidth).foreach(i => fetchPacketWire.brInfo(i).hist := final_gh)
   (0 until PredictWidth).foreach(i => fetchPacketWire.brInfo(i).predHist := if4_predHist.asTypeOf(new GlobalHistory))