RS-sep: fast wakeup become more strict again, rm one cycle fu

one cycle fu will block, fast wakeup disallow block. see last commit

src/main/scala/xiangshan/backend/fu/Fence.scala

@@ -12,7 +12,7 @@ class FenceToSbuffer extends XSBundle {
 }
 
 class Fence extends FunctionUnit(FuConfig(
-  FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false
+  FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = UncertainLatency()
 )){
 
   val sfence = IO(Output(new SfenceBundle))
@@ -45,7 +45,7 @@ class Fence extends FunctionUnit(FuConfig(
   when (state === s_sb && valid && func === FenceOpType.fencei && !sbEmpty) { state := s_icache }
   when (state === s_sb && valid && func === FenceOpType.sfence && !sbEmpty) { state := s_tlb }
   when (state === s_sb && valid && func === FenceOpType.fence  && !sbEmpty) { state := s_none }
-  when (state =/= s_sb && sbEmpty) { state := s_sb } 
+  when (state =/= s_sb && sbEmpty) { state := s_sb }
 
   assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
   io.in.ready := state === s_sb

src/main/scala/xiangshan/backend/fu/FunctionUnit.scala

@@ -161,7 +161,7 @@ object FunctionUnit extends HasXSParameter {
       UncertainLatency()
     )
 
-  val mouCfg = 
+  val mouCfg =
     FuConfig(FuType.mou, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false,
       UncertainLatency()
   )