Merge remote-tracking branch 'origin/fix-dispatch-replay' into xs-fpu

src/main/scala/xiangshan/Bundle.scala

@@ -218,6 +218,7 @@ class ExternalInterruptIO extends XSBundle {
 
 class CSRSpecialIO extends XSBundle {
   val exception = Flipped(ValidIO(new MicroOp))
+  val isInterrupt = Input(Bool())
   val memExceptionVAddr = Input(UInt(VAddrBits.W))
   val trapTarget = Output(UInt(VAddrBits.W))
   val externalInterrupt = new ExternalInterruptIO

src/main/scala/xiangshan/backend/Backend.scala

@@ -148,11 +148,12 @@ class Backend extends XSModule
   jmpExeUnit.io.csrOnly.exception.bits := roq.io.exception
   jmpExeUnit.fflags := roq.io.fflags
   jmpExeUnit.dirty_fs := roq.io.dirty_fs
-
+  jmpExeUnit.io.csrOnly.externalInterrupt := io.externalInterrupt
   jmpExeUnit.io.csrOnly.memExceptionVAddr := io.mem.exceptionAddr.vaddr
   jmpExeUnit.fenceToSbuffer <> io.mem.fenceToSbuffer
   io.mem.sfence <> jmpExeUnit.sfence
   io.mem.csr <> jmpExeUnit.tlbCsrIO
+
   io.mem.exceptionAddr.lsIdx.lsroqIdx := roq.io.exception.lsroqIdx
   io.mem.exceptionAddr.lsIdx.lqIdx := roq.io.exception.lqIdx
   io.mem.exceptionAddr.lsIdx.sqIdx := roq.io.exception.sqIdx

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -190,7 +190,16 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) exten
   // In case of replay, we need to walk back and recover preg states in the busy table.
   // We keep track of the number of entries needed to be walked instead of target position to reduce overhead
   // for 11111111, replayPosition is unuseful. We naively set Cnt to size.U
-  val dispatchReplayCnt = Mux(allReplay, size.U, Mux(maskedNeedReplay(size - 1), (dispatchPtr + replayPosition).value, (dispatchPtr - replayPosition).value))
+  val dispatchReplayCnt = Mux(
+    allReplay, size.U,
+    Mux(maskedNeedReplay(size - 1),
+      // replay makes flag flipped
+      dispatchPtr.value + replayPosition,
+      // the new replay does not change the flag
+      Mux(dispatchPtr.value <= replayPosition,
+        // but we are currently in a replay that changes the flag
+        dispatchPtr.value + (size.U - replayPosition),
+        dispatchPtr.value - replayPosition)))
   val dispatchReplayCntReg = RegInit(0.U)
   // actually, if deqIndex points to head uops and they are replayed, there's no need for extraWalk
   // however, to simplify logic, we simply let it do extra walk now

src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala

@@ -74,6 +74,7 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
   csr.io.perf <> DontCare
 
   csr.io.exception := io.csrOnly.exception
+  csr.io.isInterrupt := io.redirect.bits.isFlushPipe
   csr.io.memExceptionVAddr := io.csrOnly.memExceptionVAddr
   io.csrOnly.trapTarget := csr.io.trapTarget
   csr.io.mtip := io.csrOnly.externalInterrupt.mtip

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -177,6 +177,7 @@ class CSRIO extends FunctionUnitIO[UInt, Null](csrCfg, len=64, extIn= FuOpType()
   val cfOut = Output(new CtrlFlow)
   // from rob
   val exception = Flipped(ValidIO(new MicroOp))
+  val isInterrupt = Input(Bool())
   // for exception check
   val instrValid = Input(Bool())
   val flushPipe = Output(Bool())
@@ -637,7 +638,7 @@ class CSR extends XSModule
   val intrBitSet = intrVec.orR()
   io.interrupt := intrBitSet
   val intrNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(intrVec(i), i.U, sum))
-  val raiseIntr = intrBitSet && io.exception.valid
+  val raiseIntr = intrBitSet && io.exception.valid && io.isInterrupt
   XSDebug(raiseIntr, "interrupt: pc=0x%x, %d\n", io.exception.bits.cf.pc, intrNO)
 
   mipWire.t.m := io.mtip

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -148,7 +148,8 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
   io.redirect := DontCare
   io.redirect.valid := (state === s_idle) && (intrEnable || exceptionEnable || isFlushPipe)// TODO: add fence flush to flush the whole pipe
   io.redirect.bits.isException := intrEnable || exceptionEnable
-  io.redirect.bits.isFlushPipe := isFlushPipe
+  // reuse isFlushPipe to represent interrupt for CSR
+  io.redirect.bits.isFlushPipe := isFlushPipe || intrEnable
   io.redirect.bits.target := Mux(isFlushPipe, deqUop.cf.pc + 4.U, io.trapTarget)
   io.exception := deqUop
   XSDebug(io.redirect.valid, "generate redirect: pc 0x%x intr %d excp %d flushpp %d target:0x%x Traptarget 0x%x exceptionVec %b\n", io.exception.cf.pc, intrEnable, exceptionEnable, isFlushPipe, io.redirect.bits.target, io.trapTarget, Cat(microOp(deqPtr).cf.exceptionVec))