perf: add commit time debug

src/main/scala/xiangshan/Bundle.scala

@@ -162,10 +162,10 @@ trait HasRoqIdx { this: HasXSParameter =>
 class PerfDebugInfo extends XSBundle {
   // val fetchTime = UInt(64.W)
   val renameTime = UInt(64.W)
-  val inRoqTime = UInt(64.W)
+  val dispatchTime = UInt(64.W)
   val issueTime = UInt(64.W)
   val writebackTime = UInt(64.W)
-  val commitTime = UInt(64.W)
+  // val commitTime = UInt(64.W)
 }
 
 // CfCtrl -> MicroOp at Rename Stage
@@ -174,7 +174,7 @@ class MicroOp extends CfCtrl with HasRoqIdx {
   val src1State, src2State, src3State = SrcState()
   val lsroqIdx = UInt(LsroqIdxWidth.W)
   val diffTestDebugLrScValid = Bool()
-  val debugInfo = PerfDebugInfo()
+  val debugInfo = new PerfDebugInfo
 }
 
 class Redirect extends XSBundle with HasRoqIdx {

src/main/scala/xiangshan/backend/Backend.scala

 package xiangshan.backend
 
-import bus.simplebus.SimpleBusUC
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
-import noop.MemMMUIO
 import xiangshan._
 import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
 import xiangshan.backend.rename.Rename
@@ -16,7 +14,7 @@ import xiangshan.backend.issue.{IssueQueue, ReservationStation}
 import xiangshan.backend.regfile.{Regfile, RfWritePort}
 import xiangshan.backend.roq.Roq
 import xiangshan.mem._
-import utils.ParallelOR
+import utils._
 
 /** Backend Pipeline:
   * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
@@ -27,7 +25,7 @@ class Backend extends XSModule
     val frontend = Flipped(new FrontendToBackendIO)
     val mem = Flipped(new MemToBackendIO)
   })
-
+  val timer = GTimer()
 
   val aluExeUnits =Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
   val jmpExeUnit = Module(new JmpExeUnit)
@@ -37,9 +35,12 @@ class Backend extends XSModule
   // val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
   // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
   val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits)
-  exeUnits.foreach(_.io.exception := DontCare)
-  exeUnits.foreach(_.io.dmem := DontCare)
-  exeUnits.foreach(_.io.mcommit := DontCare)
+  exeUnits.foreach(exe => {
+    exe.io.exception := DontCare
+    exe.io.dmem := DontCare
+    exe.io.mcommit := DontCare
+    exe.io.in.bits.uop.debugInfo.issueTime := timer
+  })
 
   val decode = Module(new DecodeStage)
   val brq = Module(new Brq)
@@ -190,7 +191,7 @@ class Backend extends XSModule
     x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
   }
   decode.io.brTags <> brq.io.brTags
-  decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)) // TODO: opt this
+  decBuf.io.isWalking := Cat(roq.io.commits.map(c => c.valid && c.bits.isWalk)).orR // TODO: opt this
   decBuf.io.redirect <> redirect
   decBuf.io.in <> decode.io.out
 
@@ -204,10 +205,12 @@ class Backend extends XSModule
   rename.io.replayPregReq <> dispatch.io.replayPregReq
   dispatch.io.redirect <> redirect
   dispatch.io.fromRename <> rename.io.out
+  dispatch.io.fromRename.foreach(_.bits.debugInfo.renameTime := timer)
 
   roq.io.memRedirect <> io.mem.replayAll
   roq.io.brqRedirect <> brq.io.redirect
   roq.io.dp1Req <> dispatch.io.toRoq
+  roq.io.dp1Req.foreach(_.bits.debugInfo.dispatchTime := timer)
   dispatch.io.roqIdxs <> roq.io.roqIdxs
   io.mem.dp1Req <> dispatch.io.toLsroq
   dispatch.io.lsroqIdxs <> io.mem.lsroqIdxs
@@ -242,7 +245,22 @@ class Backend extends XSModule
 
   roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
   roq.io.exeWbResults.last := brq.io.out
-
+  roq.io.exeWbResults.foreach(_.bits.uop.debugInfo.writebackTime := timer)
+
+  val commitTime = timer
+  val renameToCommit = roq.io.commits.map(c => Mux(c.valid && !c.bits.isWalk, timer - c.bits.uop.debugInfo.renameTime, 0.U)).reduce(_ + _)
+  val dispatchToCommit = roq.io.commits.map(c => Mux(c.valid && !c.bits.isWalk, timer - c.bits.uop.debugInfo.dispatchTime, 0.U)).reduce(_ + _)
+  val issueToCommit = roq.io.commits.map(c => Mux(c.valid && !c.bits.isWalk, timer - c.bits.uop.debugInfo.issueTime, 0.U)).reduce(_ + _)
+  val writebackToCommit = roq.io.commits.map(c => Mux(c.valid && !c.bits.isWalk, timer - c.bits.uop.debugInfo.writebackTime, 0.U)).reduce(_ + _)
+  val loadDispatchToCommit = roq.io.commits.map(c => Mux(c.valid && !c.bits.isWalk && c.bits.uop.ctrl.commitType === CommitType.LOAD, timer - c.bits.uop.debugInfo.renameTime, 0.U)).reduce(_ + _)
+  val storeDispatchToCommit = roq.io.commits.map(c => Mux(c.valid && !c.bits.isWalk && c.bits.uop.ctrl.commitType === CommitType.STORE, timer - c.bits.uop.debugInfo.renameTime, 0.U)).reduce(_ + _)
+
+  XSPerf("renameToCommit", renameToCommit)
+  XSPerf("dispatchToCommit", dispatchToCommit)
+  XSPerf("issueToCommit", issueToCommit)
+  XSPerf("writebackToCommit", writebackToCommit)
+  XSPerf("loadDispatchToCommit", loadDispatchToCommit)
+  XSPerf("storeDispatchToCommit", storeDispatchToCommit)
 
   // TODO: Remove sink and source
   val tmp = WireInit(0.U)

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.rename
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import utils.XSInfo
+import utils._
 
 class Rename extends XSModule {
   val io = IO(new Bundle() {
@@ -70,13 +70,13 @@ class Rename extends XSModule {
     uop.roqIdx := DontCare
     uop.lsroqIdx := DontCare
     uop.diffTestDebugLrScValid := DontCare
+    uop.debugInfo := DontCare
   })
 
   var lastReady = WireInit(io.out(0).ready)
   // debug assert
   val outRdy = Cat(io.out.map(_.ready))
   assert(outRdy===0.U || outRdy.andR())
-  val timer = GTimer()
   for(i <- 0 until RenameWidth) {
     uops(i).cf := io.in(i).bits.cf
     uops(i).ctrl := io.in(i).bits.ctrl
@@ -120,7 +120,6 @@ class Rename extends XSModule {
 
     io.out(i).valid := io.in(i).fire()
     io.out(i).bits := uops(i)
-    io.out(i).bits.debugInfo.renameTime = timer
 
     // write rename table
     def writeRat(fp: Boolean) = {

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -65,7 +65,6 @@ class Roq extends XSModule {
 
     when(io.dp1Req(i).fire()){
       microOp(roqIdx) := io.dp1Req(i).bits
-      microOp(roqIdx).debugInfo.inRoqTime := timer
       valid(roqIdx) := true.B
       flag(roqIdx) := roqIdxExt.head(1).asBool()
       writebacked(roqIdx) := false.B
@@ -96,7 +95,6 @@ class Roq extends XSModule {
       writebacked(wbIdx) := true.B
       microOp(wbIdx).cf.exceptionVec := io.exeWbResults(i).bits.uop.cf.exceptionVec
       microOp(wbIdx).lsroqIdx := io.exeWbResults(i).bits.uop.lsroqIdx
-      microOp(wbIdx).debugInfo.writebackTime := timer
       microOp(wbIdx).ctrl.flushPipe := io.exeWbResults(i).bits.uop.ctrl.flushPipe
       microOp(wbIdx).diffTestDebugLrScValid := io.exeWbResults(i).bits.uop.diffTestDebugLrScValid
       exuData(wbIdx) := io.exeWbResults(i).bits.data
@@ -185,6 +183,17 @@ class Roq extends XSModule {
           commitUop.old_pdest,
           exuData(commitIdx)
         )
+        when (io.commits(i).valid) {
+          printf(
+            "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x\n",
+            commitUop.cf.pc,
+            commitUop.ctrl.rfWen,
+            commitUop.ctrl.ldest,
+            commitUop.pdest,
+            commitUop.old_pdest,
+            exuData(commitIdx)
+          )
+        }
         XSInfo(io.commits(i).valid && exuDebug(commitIdx).isMMIO,
           "difftest skiped pc0x%x\n",
           commitUop.cf.pc
@@ -306,6 +315,8 @@ class Roq extends XSModule {
 
   XSPerf("utilization", PopCount(valid))
   XSPerf("commitInstr", PopCount(io.commits.map(c => c.valid && !c.bits.isWalk)))
+  XSPerf("commitInstrLoad", PopCount(io.commits.map(c => c.valid && !c.bits.isWalk && c.bits.uop.ctrl.commitType === CommitType.LOAD)))
+  XSPerf("commitInstrStore", PopCount(io.commits.map(c => c.valid && !c.bits.isWalk && c.bits.uop.ctrl.commitType === CommitType.STORE)))
   XSPerf("writeback", PopCount((0 until RoqSize).map(i => valid(i) && writebacked(i))))
   XSPerf("enqInstr", PopCount(io.dp1Req.map(_.fire())))
   XSPerf("walkInstr", PopCount(io.commits.map(c => c.valid && c.bits.isWalk)))