fu: fix needFlush arguments

src/main/scala/xiangshan/backend/fu/Radix2Divider.scala

@@ -41,7 +41,7 @@ class Radix2Divider(len: Int) extends AbstractDivider(len) {
   val uopReg = RegEnable(uop, newReq)
 
   val cnt = Counter(len)
-  when (newReq && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn)) {
+  when (newReq && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn, io.flushIn)) {
     state := s_log2
   } .elsewhen (state === s_log2) {
     // `canSkipShift` is calculated as following:
@@ -87,4 +87,4 @@ class Radix2Divider(len: Int) extends AbstractDivider(len) {
 
   io.out.valid := state === s_finish
   io.in.ready := state === s_idle
-}
+}
\ No newline at end of file

src/main/scala/xiangshan/backend/fu/SRT4Divider.scala

@@ -37,7 +37,7 @@ class SRT4Divider(len: Int) extends AbstractDivider(len) {
 
   switch(state){
     is(s_idle){
-      when (io.in.fire() && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn)) {
+      when (io.in.fire() && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn, io.flushIn)) {
         state := Mux(divZero, s_finish, s_lzd)
       }
     }

src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala

@@ -47,7 +47,7 @@ class FDivSqrt extends FPUSubModule {
 
   val src1 = unbox(io.in.bits.src(0), tag, None)
   val src2 = unbox(io.in.bits.src(1), tag, None)
-  divSqrt.io.inValid := io.in.fire() && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn)
+  divSqrt.io.inValid := io.in.fire() && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn, io.flushIn)
   divSqrt.io.sqrtOp := fpCtrl.sqrt
   divSqrt.io.a := src1
   divSqrt.io.b := src2