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7c658794
编写于
1月 10, 2021
作者:
Y
YikeZhou
浏览文件
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电子邮件补丁
差异文件
Dispatch2: slightly changed readPortIndex calculating process
ReservationStation: change width of srcRegValue into (XLEN+1)
上级
2b36ef19
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
19 addition
and
17 deletion
+19
-17
src/main/scala/xiangshan/backend/FloatBlock.scala
src/main/scala/xiangshan/backend/FloatBlock.scala
+5
-4
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
+8
-7
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
+5
-5
src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
...scala/xiangshan/backend/issue/ReservationStationNew.scala
+1
-1
未找到文件。
src/main/scala/xiangshan/backend/FloatBlock.scala
浏览文件 @
7c658794
...
...
@@ -3,6 +3,7 @@ package xiangshan.backend
import
chisel3._
import
chisel3.util._
import
xiangshan._
import
utils._
import
xiangshan.backend.regfile.Regfile
import
xiangshan.backend.exu._
import
xiangshan.backend.issue.
{
ReservationStationCtrl
,
ReservationStationData
}
...
...
@@ -89,10 +90,10 @@ class FloatBlock
rsCtrl
.
io
.
enqCtrl
<>
io
.
fromCtrlBlock
.
enqIqCtrl
(
i
)
rsData
.
io
.
srcRegValue
:=
DontCare
val
s
tartIndex
=
readPortIndex
(
i
)
*
3.
U
rsData
.
io
.
srcRegValue
(
0
)
:=
fpRf
.
io
.
readPorts
(
startIndex
).
data
rsData
.
io
.
srcRegValue
(
1
)
:=
fpRf
.
io
.
readPorts
(
startIndex
+
1.
U
).
data
rsData
.
io
.
srcRegValue
(
2
)
:=
fpRf
.
io
.
readPorts
(
startIndex
+
2.
U
).
data
val
s
rcIndex
=
(
0
until
3
).
map
(
Range
(
_
,
12
,
3
).
map
(
_
.
U
))
rsData
.
io
.
srcRegValue
(
0
)
:=
fpRf
.
io
.
readPorts
(
ParallelLookUp
(
readPortIndex
(
i
),
(
0
until
4
).
map
(
_
.
U
).
zip
(
srcIndex
(
0
)))
).
data
rsData
.
io
.
srcRegValue
(
1
)
:=
fpRf
.
io
.
readPorts
(
ParallelLookUp
(
readPortIndex
(
i
),
(
0
until
4
).
map
(
_
.
U
).
zip
(
srcIndex
(
1
)))
).
data
rsData
.
io
.
srcRegValue
(
2
)
:=
fpRf
.
io
.
readPorts
(
ParallelLookUp
(
readPortIndex
(
i
),
(
0
until
4
).
map
(
_
.
U
).
zip
(
srcIndex
(
2
)))
).
data
rsData
.
io
.
redirect
<>
redirect
rsData
.
io
.
writeBackedData
<>
writeBackData
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
浏览文件 @
7c658794
...
...
@@ -76,9 +76,9 @@ class Dispatch2Fp extends XSModule {
io
.
readRf
(
3
*
i
+
1
).
addr
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc2
io
.
readRf
(
3
*
i
+
2
).
addr
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc3
}
val
readPortIndex
=
Wire
(
Vec
(
exuParameters
.
FpExuCnt
,
UInt
(
log2Ceil
(
NRFpReadPorts
-
exuParameters
.
StuCnt
)
.
W
)))
fpStaticIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
(
3
*
i
)
.
U
})
fpDynamicIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
3.
U
*
fpDynamicExuSrc
(
i
)})
val
readPortIndex
=
Wire
(
Vec
(
exuParameters
.
FpExuCnt
,
UInt
(
2
.
W
)))
fpStaticIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
i
.
U
})
fpDynamicIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
fpDynamicExuSrc
(
i
)})
/**
* Part 3: dispatch to reservation stations
...
...
@@ -87,9 +87,10 @@ class Dispatch2Fp extends XSModule {
val
enq
=
io
.
enqIQCtrl
(
i
)
enq
.
valid
:=
validVec
(
i
)
enq
.
bits
:=
io
.
fromDq
(
indexVec
(
i
)).
bits
enq
.
bits
.
src1State
:=
io
.
regRdy
(
readPortIndex
(
i
))
enq
.
bits
.
src2State
:=
io
.
regRdy
(
readPortIndex
(
i
)
+
1.
U
)
enq
.
bits
.
src3State
:=
io
.
regRdy
(
readPortIndex
(
i
)
+
2.
U
)
val
srcIndex
=
(
0
until
3
).
map
(
Range
(
_
,
12
,
3
).
map
(
_
.
U
))
enq
.
bits
.
src1State
:=
io
.
regRdy
(
ParallelLookUp
(
readPortIndex
(
i
),
(
0
until
4
).
map
(
_
.
U
).
zip
(
srcIndex
(
0
))))
enq
.
bits
.
src2State
:=
io
.
regRdy
(
ParallelLookUp
(
readPortIndex
(
i
),
(
0
until
4
).
map
(
_
.
U
).
zip
(
srcIndex
(
1
))))
enq
.
bits
.
src3State
:=
io
.
regRdy
(
ParallelLookUp
(
readPortIndex
(
i
),
(
0
until
4
).
map
(
_
.
U
).
zip
(
srcIndex
(
2
))))
XSInfo
(
enq
.
fire
(),
p
"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} "
+
p
"srcState(${enq.bits.src1State} ${enq.bits.src2State} ${enq.bits.src3State}) "
+
...
...
@@ -111,7 +112,7 @@ class Dispatch2Fp extends XSModule {
/**
* Part 5: send read port index of register file to reservation station
*/
io
.
readPortIndex
:=
readPortIndex
.
map
(
_
/
3.
U
)
io
.
readPortIndex
:=
readPortIndex
// val readPortIndexReg = Reg(Vec(exuParameters.FpExuCnt, UInt(log2Ceil(NRFpReadPorts - exuParameters.StuCnt).W)))
// val uopReg = Reg(Vec(exuParameters.FpExuCnt, new MicroOp))
// val dataValidRegDebug = Reg(Vec(exuParameters.FpExuCnt, Bool()))
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
浏览文件 @
7c658794
...
...
@@ -79,8 +79,8 @@ class Dispatch2Int extends XSModule {
io
.
readRf
(
2
*
i
+
1
).
addr
:=
io
.
fromDq
(
index
(
intReadPortSrc
(
i
))).
bits
.
psrc2
}
val
readPortIndex
=
Wire
(
Vec
(
exuParameters
.
IntExuCnt
,
UInt
(
log2Ceil
(
NRIntReadPorts
).
W
)))
intStaticIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
(
2
*
i
)
.
U
})
intDynamicIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
2.
U
*
intDynamicExuSrc
(
i
)})
intStaticIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
i
.
U
})
intDynamicIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
intDynamicExuSrc
(
i
)})
/**
* Part 3: dispatch to reservation stations
...
...
@@ -89,8 +89,8 @@ class Dispatch2Int extends XSModule {
val
enq
=
io
.
enqIQCtrl
(
i
)
enq
.
valid
:=
validVec
(
i
)
enq
.
bits
:=
io
.
fromDq
(
indexVec
(
i
)).
bits
enq
.
bits
.
src1State
:=
io
.
regRdy
(
readPortIndex
(
i
))
enq
.
bits
.
src2State
:=
io
.
regRdy
(
readPortIndex
(
i
)
+
1.
U
)
enq
.
bits
.
src1State
:=
io
.
regRdy
(
Cat
(
readPortIndex
(
i
),
0.
U
(
1.
W
)
))
enq
.
bits
.
src2State
:=
io
.
regRdy
(
Cat
(
readPortIndex
(
i
),
1.
U
(
1.
W
))
)
XSInfo
(
enq
.
fire
(),
p
"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} "
+
p
"srcState(${enq.bits.src1State} ${enq.bits.src2State}) "
+
...
...
@@ -112,7 +112,7 @@ class Dispatch2Int extends XSModule {
/**
* Part 5: send read port index of register file to reservation station
*/
io
.
readPortIndex
:=
readPortIndex
.
map
(
_
(
2
,
1
))
io
.
readPortIndex
:=
readPortIndex
// val readPortIndexReg = Reg(Vec(exuParameters.IntExuCnt, UInt(log2Ceil(NRIntReadPorts).W)))
// val uopReg = Reg(Vec(exuParameters.IntExuCnt, new MicroOp))
// val dataValidRegDebug = Reg(Vec(exuParameters.IntExuCnt, Bool()))
...
...
src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
浏览文件 @
7c658794
...
...
@@ -336,7 +336,7 @@ class ReservationStationData
val
ctrl
=
Flipped
(
new
RSCtrlDataIO
)
// read src op value
val
srcRegValue
=
Vec
(
srcNum
,
Input
(
UInt
(
XLEN
.
W
)))
val
srcRegValue
=
Vec
(
srcNum
,
Input
(
UInt
(
(
XLEN
+
1
)
.
W
)))
// broadcast selected uop to other issue queues
val
selectedUop
=
ValidIO
(
new
MicroOp
)
...
...
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