Merge pull request #330 from RISCVERS/debian-gogogo

ifu: add icacheResp.valid to the conditions of if3_prevHalfInstrMet

src/main/scala/xiangshan/frontend/IFU.scala

@@ -179,7 +179,7 @@ class IFU extends XSModule with HasIFUConst
   val if3_pendingPrevHalfInstr = if3_prevHalfInstr.valid
 
   // the previous half of RVI instruction waits until it meets its last half
-  val if3_prevHalfInstrMet = if3_pendingPrevHalfInstr && (if3_prevHalfInstr.pc + 2.U) === if3_pc && if3_valid
+  val if3_prevHalfInstrMet = if3_pendingPrevHalfInstr && (if3_prevHalfInstr.pc + 2.U) === if3_pc && if3_valid && (inLoop || io.icacheResp.valid)
   // set to invalid once consumed or redirect from backend
   val if3_prevHalfConsumed = if3_prevHalfInstrMet && if3_fire
   val if3_prevHalfFlush = if4_flush

src/test/csrc/emu.cpp

@@ -79,7 +79,6 @@ Emulator::Emulator(int argc, const char *argv[]):
   cycles(0), hascommit(0), trapCode(STATE_RUNNING)
 {
   args = parse_args(argc, argv);
-  printf("Emu compiled at %s, %s UTC\n", __DATE__, __TIME__);
 
   // srand
   srand(args.seed);
@@ -275,6 +274,7 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
       long get_img_size();
       ref_difftest_memcpy_from_dut(0x80000000, get_img_start(), get_img_size());
       ref_difftest_setregs(reg);
+      printf("The first instruction has commited. Difftest enabled. \n");
     }
 
     // difftest