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体验新版 GitCode,发现更多精彩内容 >>
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7b4994a7
编写于
7月 20, 2020
作者:
G
GouLingrui
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差异文件
Merge remote-tracking branch 'origin/fix-temp-lsu' into dev-bpu-rebase-tage
上级
eb0036a6
ae7c6ced
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
39 addition
and
16 deletion
+39
-16
debug/Makefile
debug/Makefile
+9
-9
src/main/scala/bus/simplebus/Crossbar.scala
src/main/scala/bus/simplebus/Crossbar.scala
+28
-5
src/main/scala/xiangshan/backend/exu/LsExeUnit.scala
src/main/scala/xiangshan/backend/exu/LsExeUnit.scala
+2
-2
未找到文件。
debug/Makefile
浏览文件 @
7b4994a7
...
...
@@ -20,7 +20,7 @@ cpu:
# ------------------------------------------------------------------
cputest
:
$(MAKE)
-C
$(AM_HOME)
/tests/cputest
$(ARCH)
$(EMU_ARGS)
run 2
>&1 |
tee
>
cpu.log
$(MAKE)
-C
$(AM_HOME)
/tests/cputest
$(ARCH)
$(EMU_ARGS)
run 2
>
cpu.log
cat
cpu.log |
grep
different
cat
cpu.log |
grep
IPC
...
...
@@ -28,32 +28,32 @@ cputest:
# $(MAKE) -C $(AM_HOME)/tests/bputest $(ARCH) run 2>&1 | tee > bpu.log
# cat bpu.log | grep different
bputest
:
$(MAKE)
-C
$(AM_HOME)
/tests/bputest
$(ARCH)
run 2
>&1 |
tee
>
bpu.log
$(MAKE)
-C
$(AM_HOME)
/tests/bputest
$(ARCH)
run 2
>
bpu.log
cat
bpu.log |
grep
Mbp
amtest
:
$(MAKE)
-C
$(AM_HOME)
/tests/cputest
$(ARCH)
$(SINGLETEST)
run 2
>&1 |
tee
>
test.log
$(MAKE)
-C
$(AM_HOME)
/tests/cputest
$(ARCH)
$(SINGLETEST)
run 2
>
test.log
cat
test.log |
grep
different
cat
test.log |
grep
ISU
>
isu.log
microbench
:
$(MAKE)
-C
$(AM_HOME)
/apps/microbench
$(ARCH)
mainargs
=
test
run 2>&1 |
tee
>
microbench.log
$(MAKE)
-C
$(AM_HOME)
/apps/microbench
$(ARCH)
$(EMU_ARGS)
mainargs
=
test
run 2
>
microbench.log
cat
microbench.log |
grep
IPC
microbench_train
:
$(MAKE)
-C
$(AM_HOME)
/apps/microbench
$(ARCH)
mainargs
=
train run 2>&1 |
tee
>
microbench.log
$(MAKE)
-C
$(AM_HOME)
/apps/microbench
$(ARCH)
$(EMU_ARGS)
mainargs
=
train run 2
>
microbench.log
cat
microbench.log |
grep
IPC
coremark
:
$(MAKE)
-C
$(AM_HOME)
/apps/coremark
$(ARCH)
mainargs
=
test
run 2>&1 |
tee
>
coremark.log
$(MAKE)
-C
$(AM_HOME)
/apps/coremark
$(ARCH)
$(EMU_ARGS)
mainargs
=
test
run 2
>
coremark.log
cat
coremark.log |
grep
IPC
dhrystone
:
$(MAKE)
-C
$(AM_HOME)
/apps/dhrystone
$(ARCH)
mainargs
=
test
run 2>&1 |
tee
>
dhrystone.log
$(MAKE)
-C
$(AM_HOME)
/apps/dhrystone
$(ARCH)
$(EMU_ARGS)
mainargs
=
test
run 2
>
dhrystone.log
cat
dhrystone.log |
grep
IPC
xj
:
$(MAKE)
-C
$(NANOS_HOME)
$(ARCH)
run
$(MAKE)
-C
$(NANOS_HOME)
$(ARCH)
$(EMU_ARGS)
run
xjnemu
:
$(MAKE)
-C
$(NANOS_HOME)
ARCH
=
riscv64-nemu run
...
...
@@ -74,7 +74,7 @@ xv6-debug:
$(MAKE)
-C
$(XV6_HOME)
noop 2>&1 |
tee
>
xv6.log
linux
:
$(MAKE)
-C
$(BBL_LINUX_HOME)
noop
$(MAKE)
-C
$(BBL_LINUX_HOME)
$(EMU_ARGS)
noop
# ------------------------------------------------------------------
# get disassembled test src
# ------------------------------------------------------------------
...
...
src/main/scala/bus/simplebus/Crossbar.scala
浏览文件 @
7b4994a7
/**************************************************************************************
* Copyright (c) 2020 Institute of Computing Technology, CAS
* Copyright (c) 2020 University of Chinese Academy of Sciences
*
* NutShell is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
*
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
* FIT FOR A PARTICULAR PURPOSE.
*
* See the Mulan PSL v2 for more details.
***************************************************************************************/
package
bus.simplebus
import
chisel3._
...
...
@@ -11,7 +27,7 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
val
out
=
Vec
(
addressSpace
.
length
,
new
SimpleBusUC
)
})
val
s_idle
::
s_resp
::
Nil
=
Enum
(
2
)
val
s_idle
::
s_resp
::
s_error
::
Nil
=
Enum
(
3
)
val
state
=
RegInit
(
s_idle
)
// select the output channel according to the address
...
...
@@ -22,8 +38,10 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
val
outSel
=
io
.
out
(
outSelIdx
)
val
outSelIdxResp
=
RegEnable
(
outSelIdx
,
outSel
.
req
.
fire
()
&&
(
state
===
s_idle
))
val
outSelResp
=
io
.
out
(
outSelIdxResp
)
val
reqInvalidAddr
=
io
.
in
.
req
.
valid
&&
!
outSelVec
.
asUInt
.
orR
assert
(!
io
.
in
.
req
.
valid
||
outSelVec
.
asUInt
.
orR
,
"address decode error, bad addr = 0x%x\n"
,
addr
)
when
(!(!
io
.
in
.
req
.
valid
||
outSelVec
.
asUInt
.
orR
)
||
!(!(
io
.
in
.
req
.
valid
&&
outSelVec
.
asUInt
.
andR
))){
printf
(
"[ERROR] bad addr %x, time %d\n"
,
addr
,
GTimer
())}
// assert(!io.in.req.valid || outSelVec.asUInt.orR, "address decode error, bad addr = 0x%x\n", addr)
assert
(!(
io
.
in
.
req
.
valid
&&
outSelVec
.
asUInt
.
andR
),
"address decode error, bad addr = 0x%x\n"
,
addr
)
// bind out.req channel
...
...
@@ -34,14 +52,19 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
}}
switch
(
state
)
{
is
(
s_idle
)
{
when
(
outSel
.
req
.
fire
())
{
state
:=
s_resp
}
}
is
(
s_idle
)
{
when
(
outSel
.
req
.
fire
())
{
state
:=
s_resp
}
when
(
reqInvalidAddr
)
{
state
:=
s_error
}
}
is
(
s_resp
)
{
when
(
outSelResp
.
resp
.
fire
())
{
state
:=
s_idle
}
}
is
(
s_error
)
{
when
(
io
.
in
.
resp
.
fire
()){
state
:=
s_idle
}
}
}
io
.
in
.
resp
.
valid
:=
outSelResp
.
resp
.
fire
()
io
.
in
.
resp
.
valid
:=
outSelResp
.
resp
.
fire
()
||
state
===
s_error
io
.
in
.
resp
.
bits
<>
outSelResp
.
resp
.
bits
// io.in.resp.bits.exc.get := state === s_error
outSelResp
.
resp
.
ready
:=
io
.
in
.
resp
.
ready
io
.
in
.
req
.
ready
:=
outSel
.
req
.
ready
io
.
in
.
req
.
ready
:=
outSel
.
req
.
ready
||
reqInvalidAddr
Debug
()
{
when
(
state
===
s_idle
&&
io
.
in
.
req
.
valid
)
{
...
...
src/main/scala/xiangshan/backend/exu/LsExeUnit.scala
浏览文件 @
7b4994a7
...
...
@@ -48,7 +48,7 @@ class LsExeUnit extends Exu(Exu.lsuExeUnitCfg){
Mux
(
retiringStore
,
stqData
(
stqTail
).
src3
,
src3In
),
Mux
(
retiringStore
,
stqData
(
stqTail
).
func
,
funcIn
)
)
assert
(!(
retiringStore
&&
!
stqValid
(
stqTail
)))
//
assert(!(retiringStore && !stqValid(stqTail)))
def
genWmask
(
addr
:
UInt
,
sizeEncode
:
UInt
)
:
UInt
=
{
LookupTree
(
sizeEncode
,
List
(
...
...
@@ -149,7 +149,7 @@ class LsExeUnit extends Exu(Exu.lsuExeUnitCfg){
){
retiringStore
:=
true
.
B
}
when
(
state
===
s_partialLoad
&&
retiringStore
){
when
(
dmem
.
resp
.
fire
()
&&
retiringStore
){
retiringStore
:=
false
.
B
}
...
...
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