dcache: delay wbq data update for 1 cycle (#1701)
This commit and an extra cycle for miss queue store data and mask write. For now, there are 18 missqueue entries. Each entry has a 512 bit data reg and a 64 bit mask reg. If we update writeback queue data in 1 cycle, the fanout will be at least 18x(512+64) = 10368. Now writeback queue req meta update is unchanged, however, data and mask update will happen 1 cycle after req fire or release update fire (T0). In T0, data and meta will be written to a buffer in missqueue. In T1, s_data_merge or s_data_override in each missqueue entry will be used as data and mask wen.
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