dispatch: support replay preg status

src/main/scala/xiangshan/XSCore.scala

@@ -52,10 +52,6 @@ case class XSCoreParameters
   NRFpWritePorts: Int = 8,
   LsroqSize: Int = 16,
   RoqSize: Int = 32,
-  IntDqDeqWidth: Int = 4,
-  FpDqDeqWidth: Int = 4,
-  LsDqDeqWidth: Int = 4,
-  ReplayWidth: Int = 8,
   dpParams: DispatchParameters = DispatchParameters(
     DqEnqWidth = 4,
     IntDqSize = 64,
@@ -63,7 +59,10 @@ case class XSCoreParameters
     LsDqSize = 64,
     IntDqDeqWidth = 4,
     FpDqDeqWidth = 4,
-    LsDqDeqWidth = 4
+    LsDqDeqWidth = 4,
+    IntDqReplayWidth = 4,
+    FpDqReplayWidth = 1,
+    LsDqReplayWidth = 3
   ),
   exuParameters: ExuParameters = ExuParameters(
     JmpCnt = 1,
@@ -136,11 +135,8 @@ trait HasXSParameter {
   val RoqIdxWidth = InnerRoqIdxWidth + 1
   val InnerLsroqIdxWidth = log2Up(LsroqSize)
   val LsroqIdxWidth = InnerLsroqIdxWidth + 1
-  val IntDqDeqWidth = core.IntDqDeqWidth
-  val FpDqDeqWidth = core.FpDqDeqWidth
-  val LsDqDeqWidth = core.LsDqDeqWidth
-  val ReplayWidth = core.ReplayWidth
   val dpParams = core.dpParams
+  val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth
   val exuParameters = core.exuParameters
   val NRIntReadPorts = core.NRIntReadPorts
   val NRIntWritePorts = core.NRIntWritePorts

src/main/scala/xiangshan/backend/Backend.scala

@@ -202,8 +202,7 @@ class Backend extends XSModule
   rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
   rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr
   rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
-  // TODO: connect this
-  rename.io.replayPregReq <> DontCare
+  rename.io.replayPregReq <> dispatch.io.replayPregReq
   dispatch.io.redirect <> redirect
   dispatch.io.fromRename <> rename.io.out
 

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -14,7 +14,10 @@ case class DispatchParameters
   LsDqSize: Int,
   IntDqDeqWidth: Int,
   FpDqDeqWidth: Int,
-  LsDqDeqWidth: Int
+  LsDqDeqWidth: Int,
+  IntDqReplayWidth: Int,
+  FpDqReplayWidth: Int,
+  LsDqReplayWidth: Int
 )
 
 class Dispatch extends XSModule {
@@ -43,7 +46,8 @@ class Dispatch extends XSModule {
     val fpMemRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
     val intMemRegRdy = Vec(NRMemReadPorts, Input(Bool()))
     val fpMemRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
-
+    // replay: set preg status to not ready
+    val replayPregReq = Output(Vec(ReplayWidth, new ReplayPregReq))
     // to reservation stations
     val numExist = Input(Vec(exuParameters.ExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.ExuCnt, DecoupledIO(new MicroOp))
@@ -51,9 +55,9 @@ class Dispatch extends XSModule {
   })
 
   val dispatch1 = Module(new Dispatch1)
-  val intDq = Module(new DispatchQueue(dpParams.IntDqSize, dpParams.DqEnqWidth, dpParams.IntDqDeqWidth))
-  val fpDq = Module(new DispatchQueue(dpParams.FpDqSize, dpParams.DqEnqWidth, dpParams.FpDqDeqWidth))
-  val lsDq = Module(new DispatchQueue(dpParams.LsDqSize, dpParams.DqEnqWidth, dpParams.LsDqDeqWidth))
+  val intDq = Module(new DispatchQueue(dpParams.IntDqSize, dpParams.DqEnqWidth, dpParams.IntDqDeqWidth, dpParams.IntDqReplayWidth))
+  val fpDq = Module(new DispatchQueue(dpParams.FpDqSize, dpParams.DqEnqWidth, dpParams.FpDqDeqWidth, dpParams.FpDqReplayWidth))
+  val lsDq = Module(new DispatchQueue(dpParams.LsDqSize, dpParams.DqEnqWidth, dpParams.LsDqDeqWidth, dpParams.LsDqReplayWidth))
 
   // pipeline between rename and dispatch
   // accepts all at once
@@ -78,16 +82,27 @@ class Dispatch extends XSModule {
   intDq.io.commits.zip(io.commits).map { case (dqCommit, commit) =>
     dqCommit.valid := commit.valid && dqCommit.bits.uop.ctrl.commitType === CommitType.INT
   }
+  intDq.io.replayPregReq.zipWithIndex.map { case(replay, i) =>
+    io.replayPregReq(i) <> replay
+  }
+
   fpDq.io.redirect <> io.redirect
   fpDq.io.commits <> io.commits
   fpDq.io.commits.zip(io.commits).map { case (dqCommit, commit) =>
     dqCommit.valid := commit.valid && dqCommit.bits.uop.ctrl.commitType === CommitType.FP
   }
+  fpDq.io.replayPregReq.zipWithIndex.map { case(replay, i) =>
+    io.replayPregReq(i + dpParams.IntDqReplayWidth) <> replay
+  }
+
   lsDq.io.redirect <> io.redirect
   lsDq.io.commits <> io.commits
   lsDq.io.commits.zip(io.commits).map { case (dqCommit, commit) =>
     dqCommit.valid := commit.valid && CommitType.isLoadStore(dqCommit.bits.uop.ctrl.commitType)
   }
+  lsDq.io.replayPregReq.zipWithIndex.map { case(replay, i) =>
+    io.replayPregReq(i + dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth) <> replay
+  }
 
   // Int dispatch queue to Int reservation stations
   val intDispatch = Module(new Dispatch2Int)

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -3,22 +3,23 @@ package xiangshan.backend.dispatch
 import chisel3._
 import chisel3.util._
 import utils.{XSDebug, XSError, XSInfo}
-import xiangshan.{MicroOp, Redirect, RoqCommit, XSBundle, XSModule}
+import xiangshan.{MicroOp, Redirect, ReplayPregReq, RoqCommit, XSBundle, XSModule}
 
 
-class DispatchQueueIO(enqnum: Int, deqnum: Int) extends XSBundle {
+class DispatchQueueIO(enqnum: Int, deqnum: Int, replayWidth: Int) extends XSBundle {
   val enq = Vec(enqnum, Flipped(DecoupledIO(new MicroOp)))
   val deq = Vec(deqnum, DecoupledIO(new MicroOp))
   val commits = Input(Vec(CommitWidth, Valid(new RoqCommit)))
   val redirect = Flipped(ValidIO(new Redirect))
+  val replayPregReq = Output(Vec(replayWidth, new ReplayPregReq))
 
   override def cloneType: DispatchQueueIO.this.type =
-    new DispatchQueueIO(enqnum, deqnum).asInstanceOf[this.type]
+    new DispatchQueueIO(enqnum, deqnum, replayWidth).asInstanceOf[this.type]
 }
 
 // dispatch queue: accepts at most enqnum uops from dispatch1 and dispatches deqnum uops at every clock cycle
-class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule {
-  val io = IO(new DispatchQueueIO(enqnum, deqnum))
+class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) extends XSModule {
+  val io = IO(new DispatchQueueIO(enqnum, deqnum, replayWidth))
   val indexWidth = log2Ceil(size)
 
   val s_invalid :: s_valid :: s_dispatched :: Nil = Enum(3)
@@ -127,8 +128,9 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule {
       stateEntries(i) := s_invalid
     }
 
-    XSInfo(needCancel, p"valid entry($i)(pc = ${Hexadecimal(uopEntries(i.U).cf.pc)}) " +
-      p"cancelled with roqIndex ${Hexadecimal(io.redirect.bits.roqIdx)}\n")
+    XSInfo(needCancel, p"valid entry($i)(pc = ${Hexadecimal(uopEntries(i.U).cf.pc)})" +
+      p"roqIndex 0x${Hexadecimal(uopEntries(i.U).roqIdx)} " +
+      p"cancelled with redirect roqIndex 0x${Hexadecimal(io.redirect.bits.roqIdx)}\n")
   }
 
   // replay: from s_dispatched to s_valid
@@ -168,8 +170,8 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule {
   } :+ true.B)
   val numDeq = Mux(numDeqTry > numDeqFire, numDeqFire, numDeqTry)
   // TODO: this is unaccptable since it needs to add 64 bits
-  val headMask = (1.U((size+1).W) << headIndex) - 1.U
-  val dispatchMask = (1.U((size + 1).W) << dispatchIndex) - 1.U
+  val headMask = (1.U((size+1).W) << headIndex).asUInt() - 1.U
+  val dispatchMask = (1.U((size + 1).W) << dispatchIndex).asUInt() - 1.U
   val mask = headMask ^ dispatchMask
   val replayMask = Mux(headDirection === dispatchDirection, mask, ~mask)
   val numReplay = PopCount((0 until size).map(i => needReplay(i) & replayMask(i)))