rename: handle mv inst with ldest=0 or ldest=lsrc

decode: slightly change def of `isMove`
[TODO] handle mv inst with lsrc=0

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -503,12 +503,14 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   fpDecoder.io.instr := ctrl_flow.instr
   cs.fpu := fpDecoder.io.fpCtrl
 
+  val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr
+
   // read src1~3 location
   cs.lsrc(0) := Mux(ctrl_flow.instr === LUI, 0.U,ctrl_flow.instr(RS1_MSB,RS1_LSB))
   cs.lsrc(1) := ctrl_flow.instr(RS2_MSB,RS2_LSB)
   cs.lsrc(2) := ctrl_flow.instr(RS3_MSB,RS3_LSB)
   // read dest location
-  cs.ldest := Mux(cs.fpWen || cs.rfWen, ctrl_flow.instr(RD_MSB,RD_LSB), 0.U)
+  cs.ldest := Mux((cs.fpWen || cs.rfWen) && !(isMove && ctrl_flow.instr(RS1_MSB,RS1_LSB) === ctrl_flow.instr(RD_MSB,RD_LSB)), ctrl_flow.instr(RD_MSB,RD_LSB), 0.U)
 
   // fill in exception vector
   cf_ctrl.cf.exceptionVec := io.enq.ctrl_flow.exceptionVec
@@ -534,9 +536,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
     }
   ))
 
-  cs.isMove := BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr && 
-    cs.lsrc(0) =/= 0.U && cs.ldest =/= 0.U && 
-    cs.lsrc(0) =/= cs.ldest /* TODO these special Move instructions can be optimized */
+  cs.isMove := isMove && cs.lsrc(0) =/= 0.U /* TODO these special Move instructions can be optimized */
 
   cf_ctrl.ctrl := cs
 

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -195,7 +195,7 @@ class Rename(implicit p: Parameters) extends XSModule {
         // calculate meEnable
         meEnable(i) := isMove(i) && !(io.renameBypass.lsrc1_bypass(i-1).orR | psrc_cmp(i-1).orR | isMax.get(uops(i).psrc(0)))
       }
-      uops(i).eliminatedMove := meEnable(i)
+      uops(i).eliminatedMove := meEnable(i) || (uops(i).ctrl.isMove && uops(i).ctrl.ldest === 0.U)
   
       // send psrc of eliminated move instructions to free list and label them as eliminated
       when (meEnable(i)) {