Svinval: implement Svinval

* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

src/main/scala/xiangshan/Parameters.scala

@@ -35,6 +35,7 @@ case class XSCoreParameters
   XLEN: Int = 64,
   HasMExtension: Boolean = true,
   HasCExtension: Boolean = true,
+  HasSvinvalExtension: Boolean = false,
   HasDiv: Boolean = true,
   HasICache: Boolean = true,
   HasDCache: Boolean = true,
@@ -177,6 +178,7 @@ trait HasXSParameter {
 
   val HasMExtension = coreParams.HasMExtension
   val HasCExtension = coreParams.HasCExtension
+  val HasSvinvalExtension = coreParams.HasSvinvalExtension
   val HasDiv = coreParams.HasDiv
   val HasIcache = coreParams.HasICache
   val HasDcache = coreParams.HasDCache

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -294,6 +294,17 @@ object FDivSqrtDecode extends DecodeConstants {
   )
 }
 
+/**
+ * Svinval extension Constants
+ */
+object SvinvalDecode extends DecodeConstants {
+  val table: Array[(BitPat, List[BitPat])] = Array(
+  SINVAL_VMA        ->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.sfence, N, N, N, N, N, N, N, SelImm.IMM_X),
+  SFENCE_W_INVAL    ->List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.fence, FenceOpType.nofence, N, N, N, Y, N, N, N, SelImm.IMM_X),
+  SFENCE_INVAL_IR   ->List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, Y, N, SelImm.IMM_X)
+  )
+}
+
 /**
  * XiangShan Trap Decode constants
  */
@@ -419,6 +430,8 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
 
   var decode_table = XDecode.table ++ FDecode.table ++ FDivSqrtDecode.table ++ X64Decode.table ++ XSTrapDecode.table
 
+  if(HasSvinvalExtension) decode_table = decode_table ++ SvinvalDecode.table
+
   // output
   cf_ctrl.cf := ctrl_flow
   val cs = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table)

src/main/scala/xiangshan/backend/decode/Instructions.scala

@@ -851,5 +851,8 @@ object Instructions {
   def FMV_X_S            = BitPat("b111000000000?????000?????1010011")
   def FMV_S_X            = BitPat("b111100000000?????000?????1010011")
   def FENCE_TSO          = BitPat("b100000110011?????000?????0001111")
+  def SINVAL_VMA         = BitPat("b0001011??????????000000001110011")
+  def SFENCE_W_INVAL     = BitPat("b00011000000000000000000001110011")
+  def SFENCE_INVAL_IR    = BitPat("b00011000000100000000000001110011")
   def PAUSE              = BitPat("b00000001000000000000000000001111")
 }

src/main/scala/xiangshan/backend/fu/Fence.scala

@@ -39,7 +39,7 @@ class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
     io.in.bits.src(0)
   )
 
-  val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: Nil = Enum(5)
+  val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: s_nofence :: Nil = Enum(6)
   val state = RegInit(s_idle)
   /* fsm
    * s_idle    : init state, send sbflush
@@ -47,6 +47,7 @@ class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
    * s_tlb   : flush tlb, just hold one cycle
    * s_icache: flush icache, just hold one cycle
    * s_fence : do nothing, for timing optimiaztion
+   * s_nofence: do nothing , for Svinval extension
    */
 
   val sbuffer = toSbuffer.flushSb
@@ -66,6 +67,7 @@ class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
   when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache }
   when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb }
   when (state === s_wait && func === FenceOpType.fence  && sbEmpty) { state := s_fence }
+  when (state === s_wait && func === FenceOpType.nofence  && sbEmpty) { state := s_nofence }
   when (state =/= s_idle && state =/= s_wait) { state := s_idle }
 
   io.in.ready := state === s_idle

src/main/scala/xiangshan/package.scala

@@ -200,6 +200,7 @@ package object xiangshan {
     def fence  = "b10000".U
     def sfence = "b10001".U
     def fencei = "b10010".U
+    def nofence= "b00000".U
   }
 
   object ALUOpType {