Merge branch 'clean-up' into 'master'

Clean up

See merge request projectn/noop!23

src/main/scala/bus/simplebus/ToAXI4.scala

@@ -58,25 +58,6 @@ class SimpleBus2AXI4Converter[OT <: AXI4Lite](outType: OT) extends Module {
   axi.w .valid := mem.isWrite() && !wAck
   mem.req.ready  := Mux(mem.req.bits.isWrite(), !wAck && axi.w.ready, axi.ar.ready)
 
-  Debug(false){
-    printf("[CVT] isWrite %x wAck %x wr %x arr %x addr %x\n", mem.req.bits.isWrite(), wAck, axi.w.ready, axi.ar.ready, mem.req.bits.addr)
-  }
-
-  Debug(false){
-    when((ar.addr(31,4) === "h8010f00".U)&&(axi.ar.valid || axi.aw.valid)){
-      printf("[AXI] TIME %d addr: %x arv %x awv %x\n", GTimer(), ar.addr, axi.ar.valid, axi.aw.valid)
-    }
-  }
-
-  Debug(false){
-    when((w.data(31,0) === "h18be6784".U)&& axi.w.valid){
-      printf("[AXI] TIME %d wdata: %x wr: %x\n", GTimer(), w.data, axi.w.ready)
-    }
-    when((w.data(63,32) === "h18be6784".U)&& axi.w.valid){
-      printf("[AXI] TIME %d wdata: %x wr: %x\n", GTimer(), w.data, axi.w.ready)
-    }
-  }
-
   axi.r.ready  := mem.resp.ready
   axi.b.ready  := mem.resp.ready
   mem.resp.valid  := Mux(wen, axi.b.valid, axi.r.valid)

src/main/scala/noop/Cache.scala

@@ -79,11 +79,6 @@ sealed class CacheStage1(ro: Boolean, name: String, userBits: Int = 0) extends C
   })
 
   if (ro) when (io.in.fire()) { assert(!io.in.bits.isWrite()) }
-  Debug(false){
-    when(io.in.fire()){
-      printf("[L1$] cache stage1, addr in: %x\n", io.in.bits.addr)
-    }
-  }
 
   // read meta array and data array
   List(io.metaReadBus, io.dataReadBus).map { case x => {
@@ -127,9 +122,6 @@ sealed class CacheStage2(ro: Boolean, name: String, userBits: Int = 0) extends C
   io.out.bits.meta.tag := meta.tag
   io.out.bits.meta.dirty := dirty && io.in.valid
   io.out.bits.req <> io.in.bits.req
-  Debug(){
-    printf("[L1$] stage 2: addr %x, io.in.valid: %x, io.in.ready: %x, io.out.valid: %x, io.out.ready: %x\n", req.addr, io.in.valid, io.in.ready, io.out.valid, io.out.ready)
-  }
   io.out.valid := io.in.valid
   io.in.ready := !io.in.valid || io.out.fire()
 }
@@ -161,7 +153,7 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends C
   val dataHitWriteBus = WireInit(0.U.asTypeOf(CacheDataArrayWriteBus()))
   val metaHitWriteBus = WireInit(0.U.asTypeOf(CacheMetaArrayWriteBus()))
   val hitWrite = hit && req.isWrite()
-  val dataMerge = (dataRead & ~wordMask) | (req.wdata & wordMask)
+  val dataMerge = MaskData(dataRead, req.wdata, wordMask)
   dataHitWriteBus.req.valid := hitWrite
   dataHitWriteBus.req.bits.idx := addr.index
   dataHitWriteBus.req.bits.data.data := dataMerge
@@ -212,12 +204,6 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends C
   val readingFirst = !afterFirstRead && io.mem.resp.fire() && (state === s_memReadResp)
   val inRdataRegDemand = RegEnable(io.mem.resp.bits.rdata, readingFirst)
 
-  Debug(){
-    when(io.mem.req.valid && io.mem.req.ready){
-      printf("[L1$] mem access addr: %x\n", io.mem.req.bits.addr)
-    }
-  }
-
   switch (state) {
     is (s_idle) {
       afterFirstRead := false.B
@@ -239,15 +225,12 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends C
         afterFirstRead := true.B
 
         val inRdata = if (!ro) {
-          val rdataMergeWrite = (rdata & ~wordMask) | (req.wdata & wordMask)
+          val rdataMergeWrite = MaskData(rdata, req.wdata, wordMask)
           Mux(readingFirst, rdataMergeWrite, rdata)
         } else rdata
 
         dataRefillWriteBus.req.bits.data.data := inRdata
         dataRefillWriteBus.req.bits.wordIndex := readBeatCnt.value
-        Debug(){
-          printf("[L1$] mem access data : %x index: %x\n", dataRefillWriteBus.req.bits.data.data, dataRefillWriteBus.req.bits.wordIndex)
-        }
 
         readBeatCnt.inc()
         when (io.mem.resp.bits.isReadLast()) { state := s_wait_resp }

src/main/scala/noop/EXU.scala

@@ -26,10 +26,6 @@ class EXU(implicit val p: NOOPConfig) extends NOOPModule {
   val fuValids = Wire(Vec(FuType.num, Bool()))
   (0 until FuType.num).map (i => fuValids(i) := (fuType === i.U) && io.in.valid && !io.flush)
 
-  // when(io.in.valid){
-  //   printf("EXv %b %b %b %b %x %x\n", fuValids(0), fuValids(1), fuValids(2), fuValids(3), fuType, io.flush)
-  // }
-
   val alu = Module(new ALU)
   val aluOut = alu.access(valid = fuValids(FuType.alu), src1 = src1, src2 = src2, func = fuOpType)
   alu.io.cfIn := io.in.bits.cf

src/main/scala/noop/IDU.scala

@@ -18,12 +18,6 @@ class IDU extends NOOPModule with HasInstrType {
   val instrType :: fuType :: fuOpType :: Nil = // insert Instructions.DecodeDefault when interrupt comes
     Instructions.DecodeDefault.zip(decodeList).map{case (intr, dec) => Mux(hasIntr, intr, dec)}
 
-  Debug(){
-    when(io.out.valid){
-      printf("[IDU] pc: %x instrType: %x fuType: %x fuOpType: %x\n", io.in.bits.pc, instrType, fuType, fuOpType)
-    }
-  }
-
   io.out.bits := DontCare
 
   io.out.bits.ctrl.fuType := fuType

src/main/scala/noop/IFU.scala

@@ -35,14 +35,7 @@ class IFU extends NOOPModule with HasResetVector {
   bp1.io.in.pc.bits := npc  // predict one cycle early
   bp1.io.flush := io.redirect.valid
 
-  //val bp2 = Module(new BPU2)
-  //bp2.io.in.bits := io.out.bits
-  //bp2.io.in.valid := io.imem.resp.fire()
-
-  when (pcUpdate) { 
-    pc := npc 
-    // printf("[IF1] pc=%x\n", pc)
-  }
+  when (pcUpdate) { pc := npc }
 
   io.flushVec := Mux(io.redirect.valid, "b1111".U, 0.U)
   io.bpFlush := false.B
@@ -63,12 +56,6 @@ class IFU extends NOOPModule with HasResetVector {
   io.out.bits.pnpc := io.imem.resp.bits.user
   io.out.valid := io.imem.resp.valid && !io.flushVec(0)
 
-  Debug(){
-    when (io.out.fire()) {
-          printf("[IF1] pc=%x inst=%x\n", io.out.bits.pc, io.out.bits.instr)
-    }
-  }
-
   BoringUtils.addSource(BoolStopWatch(io.imem.req.valid, io.imem.resp.fire()), "perfCntCondMimemStall")
   BoringUtils.addSource(io.flushVec.orR, "perfCntCondMifuFlush")
 }

src/main/scala/noop/ISU.scala

@@ -97,11 +97,5 @@ class ISU(implicit val p: NOOPConfig) extends NOOPModule with HasRegFileParamete
 
   if (!p.FPGAPlatform) {
     BoringUtils.addSource(VecInit((0 to NRReg-1).map(i => rf.read(i.U))), "difftestRegs")
-
-  Debug(){
-    when(io.out.fire()){
-        printf("[ISU] pc=%x, inst=%x rfwen=%b\n", io.out.bits.cf.pc, io.out.bits.cf.instr, io.out.bits.ctrl.rfWen)
-      }
-    }
   }
 }

src/main/scala/noop/WBU.scala

@@ -19,16 +19,7 @@ class WBU(implicit val p: NOOPConfig) extends Module {
 
   io.redirect := io.in.bits.decode.cf.redirect
   io.redirect.valid := io.in.bits.decode.cf.redirect.valid && io.in.valid
-  
-  Debug(){
-    when(io.wb.rfWen){
-      printf("[WBU] pc:%x reg: %d, data: %x commit type: %x uncache: %x\n", io.in.bits.decode.cf.pc, io.wb.rfDest, io.wb.rfData, io.in.bits.decode.ctrl.fuType, io.in.bits.isMMIO)
-    }
-  }
 
-  // when(io.in.valid){
-  //   printf("[WBU] pc:%x reg: %d, data: %x commit type: %x %x\n", io.in.bits.decode.cf.pc, io.wb.rfDest, io.wb.rfData, io.in.bits.decode.ctrl.fuType, io.wb.rfWen)
-  // }
   BoringUtils.addSource(io.in.valid, "perfCntCondMinstret")
   if (!p.FPGAPlatform) {
     BoringUtils.addSource(RegNext(io.in.valid), "difftestCommit")

src/main/scala/noop/fu/ALU.scala

@@ -108,12 +108,6 @@ class ALU extends NOOPModule {
   io.in.ready := true.B
   io.out.valid := valid
 
-  Debug(){
-    when(io.out.valid){
-      printf("[ALU] func: %b 1: %x, 2: %x, out: %x\n", func, src1, src2, io.out.bits)
-    }
-  }
-
   val bpuUpdateReq = WireInit(0.U.asTypeOf(new BPUUpdateReq))
   bpuUpdateReq.valid := valid && isBru
   bpuUpdateReq.pc := io.cfIn.pc

src/main/scala/noop/fu/LSU.scala

@@ -93,46 +93,6 @@ class LSU extends NOOPModule {
   io.mmio.req.valid := valid && (state === s_idle) && mmio
   io.mmio.resp.ready := true.B
 
-  Debug(true){
-    // when(isStore && (dmem.req.bits.wdata(31,0) === "h00003f00".U)){
-    //   printf("TIME %d addr: %x dmem.req.bits.wdata %x, dmem.req.bits.wmask %x\n", GTimer(), addr, dmem.req.bits.wdata, dmem.req.bits.wmask)
-    // }
-    // when(isStore && (dmem.req.bits.wdata(31,0) === "h8018b120".U)){
-    //   printf("TIME %d addr: %x dmem.req.bits.wdata %x, dmem.req.bits.wmask %x\n", GTimer(), addr, dmem.req.bits.wdata, dmem.req.bits.wmask)
-    // }
-
-    // when(isStore && (addr(31,0) === "h40600000".U)){
-    //   printf("TIME %d addr: %x dmem.req.bits.wdata %x, dmem.req.bits.wmask %x im %x\n", GTimer(), addr, dmem.req.bits.wdata, dmem.req.bits.wmask, mmio)
-    // }
-
-  }
-
-  Debug(){
-    when(dmem.req.fire()){
-      printf("[LSU] (req) addr:%x data:%x wen:%b\n",addr, dmem.req.bits.wdata, isStore)
-    } 
-  
-  
-    when(dmem.resp.fire()){
-      printf("[LSU] (resp) addr:%x data:%x wen:%b\n",addr, io.out.bits, isStore)
-      // printf("%x\n", rdata)
-    }
-  
-    when(io.mmio.req.fire()){
-      printf("[LSU] (mmio req) addr:%x data:%x wen:%b\n",addr, dmem.req.bits.wdata, isStore)
-    } 
-  
-  
-    when(io.mmio.resp.fire()){
-      printf("[LSU] (mmio resp) addr:%x data:%x wen:%b\n",addr, io.out.bits, isStore)
-      // printf("%x\n", rdata)
-    }
-  
-    when(state===s_partialLoad){
-      printf("[LSU] (partialLoad) addr:%x data:%x wen:%b\n",addr, io.out.bits, isStore)
-    }
-  }
-  
   io.out.valid := Mux(isStore && !mmio, state === s_partialLoad, Mux(partialLoad, state === s_partialLoad,
     Mux(mmio, io.mmio.resp.fire(), dmem.resp.fire() && (state === s_wait_resp))))
   io.in.ready := (state === s_idle)

src/main/scala/utils/DiffTest.scala

-package utils
-
-import chisel3._
-import chisel3.util._
-
-class DiffTestIO extends Bundle {
-  val r = Output(Vec(32, UInt(64.W)))
-  val commit = Output(Bool())
-  val thisPC = Output(UInt(64.W))
-  val isMMIO = Output(Bool())
-  val intrNO = Output(UInt(64.W))
-}

src/test/csrc/device.cpp

@@ -3,18 +3,12 @@
 #include <SDL2/SDL.h>
 
 void send_key(uint8_t, bool);
-uint32_t read_key(void);
 void init_sdl(void);
-void update_screen(void *vmem);
-uint32_t screen_size(void);
 void set_abort(void);
 
-int uart_getc(void);
-void uart_putc(char c);
 void init_uart(void);
 
 static struct timeval boot = {};
-static uint32_t vmem[800 * 600];
 
 void init_device(void) {
   init_sdl();
@@ -54,44 +48,3 @@ uint32_t uptime(void) {
 
   return s * 1000 + (us + 500) / 1000;
 }
-
-extern "C" void put_pixel(uint32_t pixel) {
-  static int i = 0;
-  vmem[i++] = pixel;
-  if (i >= 800 * 600) i = 0;
-}
-
-extern "C" void vmem_sync(void) {
-  update_screen(vmem);
-}
-
-extern "C" void device_helper(
-    uint8_t req_wen, uint64_t req_addr, uint64_t req_wdata, uint8_t req_wmask, uint64_t *resp_rdata) {
-  switch (req_addr) {
-      // read uartlite stat register
-    case 0x40600008: *resp_rdata = 0x01; break; // set UARTLITE_RX_VALID
-      // read uartlite ctrl register
-    case 0x4060000c: *resp_rdata = 0; break;
-      // write uartlite tx fifo
-    case 0x40600004: if (req_wen) uart_putc((char)req_wdata); break;
-      // read uartlite rx fifo
-    //case 0x40600000: *resp_rdata = uart_getc(); break;
-      // read RTC
-    case 0x40700000: *resp_rdata = uptime(); break;
-      // read key
-    case 0x40900000: *resp_rdata = read_key(); break;
-      // read screen size
-    case 0x40800000: *resp_rdata = screen_size(); break;
-      // write vga sync
-    case 0x40800004: update_screen(vmem); break;
-    default:
-      if (req_addr >= 0x40000000 && req_addr < 0x40400000 && req_wen) {
-        // write to vmem
-        vmem[(req_addr - 0x40000000) / sizeof(uint64_t)] = req_wdata;
-      }
-      else {
-        eprintf("bad address = 0x%08x, wen = %d\n", (uint32_t)req_addr, req_wen);
-        assert(0);
-      }
-  }
-}

src/test/csrc/vga.cpp

@@ -7,22 +7,25 @@
 #define SCREEN_H 600
 #define SCREEN_W 800
 
+static uint32_t vmem[800 * 600];
 
 static SDL_Window *window;
 static SDL_Renderer *renderer;
 static SDL_Texture *texture;
 
-void update_screen(void *vmem) {
+extern "C" void put_pixel(uint32_t pixel) {
+  static int i = 0;
+  vmem[i++] = pixel;
+  if (i >= 800 * 600) i = 0;
+}
+
+extern "C" void vmem_sync(void) {
   SDL_UpdateTexture(texture, NULL, vmem, SCREEN_W * sizeof(uint32_t));
   SDL_RenderClear(renderer);
   SDL_RenderCopy(renderer, texture, NULL, NULL);
   SDL_RenderPresent(renderer);
 }
 
-uint32_t screen_size(void) {
-  return ((SCREEN_W) << 16) | (SCREEN_H);
-}
-
 void init_sdl() {
   SDL_Init(SDL_INIT_VIDEO);
   SDL_CreateWindowAndRenderer(SCREEN_W, SCREEN_H, 0, &window, &renderer);

src/test/scala/top/NOOPSim.scala

@@ -9,7 +9,14 @@ import chisel3.util.experimental.BoringUtils
 
 import bus.axi4._
 import device.AXI4RAM
-import utils.DiffTestIO
+
+class DiffTestIO extends Bundle {
+  val r = Output(Vec(32, UInt(64.W)))
+  val commit = Output(Bool())
+  val thisPC = Output(UInt(64.W))
+  val isMMIO = Output(Bool())
+  val intrNO = Output(UInt(64.W))
+}
 
 class NOOPSimTop extends Module {
   val io = IO(new Bundle{

src/test/scala/top/SimMMIO.scala

@@ -6,19 +6,6 @@ import chisel3.util._
 import bus.simplebus._
 import device._
 
-class DeviceHelper extends BlackBox {
-  val io = IO(new Bundle {
-    val clk = Input(Clock())
-    val reset = Input(Bool())
-    val reqValid = Input(Bool())
-    val reqWen = Input(Bool())
-    val reqAddr = Input(UInt(64.W))
-    val reqWdata = Input(UInt(64.W))
-    val reqWmask = Input(UInt(8.W))
-    val respRdata = Output(UInt(64.W))
-  })
-}
-
 class SimMMIO extends Module {
   val io = IO(new Bundle {
     val rw = Flipped(new SimpleBusUC)
@@ -45,20 +32,4 @@ class SimMMIO extends Module {
   vga.io.vga := DontCare
 
   io.mtip := timer.io.extra.get.mtip
-
-  //val helper = Module(new DeviceHelper)
-  //val helperIO = xbar.io.out(0)
-  //helper.io.clk := clock
-  //helper.io.reset := reset.asBool
-  //helper.io.reqValid := helperIO.req.valid
-  //helper.io.reqWen := helperIO.isWrite()
-  //helper.io.reqAddr := helperIO.req.bits.addr
-  //helper.io.reqWdata := helperIO.req.bits.wdata
-  //helper.io.reqWmask := helperIO.req.bits.wmask
-  //helperIO.resp.bits.rdata := helper.io.respRdata
-  //helperIO.resp.bits.cmd := 0.U
-  //helperIO.resp.bits.user := 0.U
-
-  //helperIO.req.ready := true.B
-  //helperIO.resp.valid := RegNext(helperIO.req.valid)
 }

src/test/vsrc/device.v

-import "DPI-C" function void device_helper
-(
-  input  bit    req_wen,
-  input  longint    req_addr,
-  input  longint    req_wdata,
-  input  byte   req_wmask,
-  output longint    resp_rdata
-);
-
-module DeviceHelper(
-  input         clk,
-  input         reset,
-  input         reqValid,
-  input         reqWen,
-  input  [63:0] reqAddr,
-  input  [63:0] reqWdata,
-  input  [7:0]  reqWmask,
-  output [63:0] respRdata
-);
-
-  always @(posedge clk) begin
-    if (reqValid && !reset) device_helper(reqWen, reqAddr, reqWdata, reqWmask, respRdata);
-  end
-
-endmodule