csr: delay fflags and dirty_fs for better timing (#1341)

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -769,11 +769,11 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   ))
   MaskedRegMap.generate(fixMapping, addr, rdataFix, wen && permitted, wdataFix)
 
-  when (csrio.fpu.fflags.valid) {
-    fcsr := fflags_wfn(update = true)(csrio.fpu.fflags.bits)
+  when (RegNext(csrio.fpu.fflags.valid)) {
+    fcsr := fflags_wfn(update = true)(RegNext(csrio.fpu.fflags.bits))
   }
   // set fs and sd in mstatus
-  when (csrw_dirty_fp_state || csrio.fpu.dirty_fs) {
+  when (csrw_dirty_fp_state || RegNext(csrio.fpu.dirty_fs)) {
     val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
     mstatusNew.fs := "b11".U
     mstatusNew.sd := true.B

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -600,8 +600,8 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   }
 
   // sync fflags/dirty_fs to csr
-  io.csr.fflags := fflags
-  io.csr.dirty_fs := dirty_fs
+  io.csr.fflags := RegNext(fflags)
+  io.csr.dirty_fs := RegNext(dirty_fs)
 
   // commit branch to brq
   val cfiCommitVec = VecInit(io.commits.valid.zip(io.commits.info.map(_.commitType)).map{case(v, t) => v && CommitType.isBranch(t)})