dcache: parameterize alias bits (WIP)

It seems there is something wrong with 32KB dcache default config

src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala

@@ -138,6 +138,7 @@ trait HasDCacheParameters extends HasL1CacheParameters {
   val DCacheTagOffset = DCacheAboveIndexOffset min DCacheSameVPAddrLength
   val DCacheLineOffset = DCacheSetOffset
   val DCacheIndexOffset = DCacheBankOffset
+  val DCacheAliasBits = DCacheAboveIndexOffset - DCacheTagOffset
 
   def addr_to_dcache_bank(addr: UInt) = {
     require(addr.getWidth >= DCacheSetOffset)
@@ -159,6 +160,14 @@ trait HasDCacheParameters extends HasL1CacheParameters {
     data(DCacheSRAMRowBytes * (bank + 1) - 1, DCacheSRAMRowBytes * bank)
   }
 
+  def addr_to_alias_bit(addr: UInt): UInt = {
+    if(DCacheAliasBits > 0) {
+      addr(DCacheAboveIndexOffset - 1, DCacheTagOffset)
+    } else {
+      0.U // DontCare
+    }
+  }
+
   def arbiter[T <: Bundle](
     in: Seq[DecoupledIO[T]],
     out: DecoupledIO[T],

src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala

@@ -332,7 +332,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule {
   )._2
   io.mem_acquire.bits := Mux(full_overwrite, acquirePerm, acquireBlock)
   // resolve cache alias by L2
-  io.mem_acquire.bits.user.lift(AliasKey).foreach( _ := req.vaddr(13, 12))
+  io.mem_acquire.bits.user.lift(AliasKey).foreach( _ := addr_to_alias_bit(req.vaddr))
   // trigger prefetch
   io.mem_acquire.bits.user.lift(PrefetchKey).foreach(_ := true.B)
   // prefer not to cache data in L2 by default
@@ -389,7 +389,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule {
   }
   refill.meta.coh := ClientMetadata(missCohGen(req.cmd, grant_param, isDirty))
   refill.error := error
-  refill.alias := req.vaddr(13, 12) // TODO
+  refill.alias := addr_to_alias_bit(req.vaddr)
 
   io.main_pipe_req.valid := !s_mainpipe_req && w_grantlast
   io.main_pipe_req.bits := DontCare

src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala

@@ -148,7 +148,7 @@ class ProbeQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule w
   req.source := io.mem_probe.bits.source
   req.opcode := io.mem_probe.bits.opcode
   req.addr := io.mem_probe.bits.address
-  if(DCacheAboveIndexOffset > DCacheTagOffset) {
+  if(DCacheAliasBits > 0) {
     // have alias problem, extra alias bits needed for index
     req.vaddr := Cat(
       io.mem_probe.bits.address(PAddrBits - 1, DCacheAboveIndexOffset), // dontcare