Merge pull request #35 from RISCVERS/dev-xs-execution

Roq: add log & bug fix

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -3,6 +3,7 @@ package xiangshan.backend.roq
 import chisel3._
 import chisel3.util._
 import xiangshan._
+import xiangshan.utils._
 import chisel3.util.experimental.BoringUtils
 
 // A "just-enough" Roq
@@ -42,18 +43,24 @@ class Roq(implicit val p: XSConfig) extends XSModule {
 
   // Dispatch
   val validDispatch = VecInit((0 until RenameWidth).map(io.dp1Req(_).valid)).asUInt
+  XSDebug("(ready, valid): ")
   for(i <- 0 until RenameWidth){
     val offset = if(i==0) 0.U else PopCount(validDispatch(i-1,0))
     when(io.dp1Req(i).fire()){
       microOp(ringBufferHead+offset) := io.dp1Req(i).bits
       valid(ringBufferHead+offset) := true.B
+      writebacked(ringBufferHead+offset) := false.B
     }
     io.dp1Req(i).ready := ringBufferAllowin && !valid(ringBufferHead+offset) && state === s_idle
     io.roqIdxs(i) := ringBufferHeadExtended+offset
+    XSDebug(){printf("(%d, %d) ", io.dp1Req(i).ready, io.dp1Req(i).valid)}
   }
+  XSDebug(){printf("\n")}
+
   val firedDispatch = VecInit((0 until CommitWidth).map(io.dp1Req(_).fire())).asUInt
-  when(validDispatch.orR){
-    ringBufferHeadExtended := ringBufferHeadExtended + PopCount(validDispatch)
+  when(firedDispatch.orR){
+    ringBufferHeadExtended := ringBufferHeadExtended + PopCount(firedDispatch)
+    XSInfo("dispatched %d insts\n", PopCount(firedDispatch))
   }
 
   // Writeback
@@ -64,14 +71,19 @@ class Roq(implicit val p: XSConfig) extends XSModule {
       exuDebug(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.debug
     }
   }
+  val firedWriteback = VecInit((0 until exuConfig.ExuCnt).map(io.exeWbResults(_).fire())).asUInt
+  when(PopCount(firedWriteback) > 0.U){
+    XSInfo("writebacked %d insts\n", PopCount(firedWriteback))
+  }
 
   // Commit uop to Rename
   for(i <- 0 until CommitWidth){
     when(state === s_idle){
-      io.commits(i).valid := valid(ringBufferTail+i.U) && writebacked(ringBufferTail+i.U)
+      val canCommit = if(i!=0) io.commits(i-1).valid else true.B
+      io.commits(i).valid := valid(ringBufferTail+i.U) && writebacked(ringBufferTail+i.U) && canCommit
       io.commits(i).bits.uop := microOp(ringBufferTail+i.U)
       when(microOp(i).ctrl.rfWen){ archRF(microOp(i).ctrl.ldest) := exuData(i) }
-      when(valid(ringBufferTail+i.U)){valid(ringBufferTail+i.U) := false.B}//FIXIT
+      when(io.commits(i).valid){valid(ringBufferTail+i.U) := false.B}
     }.otherwise{//state === s_walk
       io.commits(i).valid := valid(ringBufferWalk+i.U) && writebacked(ringBufferWalk+i.U)
       io.commits(i).bits.uop := microOp(ringBufferWalk+i.U)
@@ -85,6 +97,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     ringBufferTailExtended := ringBufferTailExtended + PopCount(validCommit)
   }
   val retireCounter = Mux(state === s_idle, PopCount(validCommit), 0.U)
+  // TODO: commit store
+  XSInfo(retireCounter > 0.U, "retired %d insts\n", retireCounter)
 
   val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk + i.U) === ringBufferWalkTarget).reduce(_||_)
 
@@ -94,9 +108,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
       state := s_idle
     }
     ringBufferWalkExtended := ringBufferWalkExtended + CommitWidth.U
-    // Debug(){
-      printf("[ROQ] rolling back: head %d tail %d walk %d\n", ringBufferHead, ringBufferTail, ringBufferWalk)
-    // }
+    XSInfo("rolling back: head %d tail %d walk %d\n", ringBufferHead, ringBufferTail, ringBufferWalk)
   }
 
   when(io.brqRedirect.valid){
@@ -110,6 +122,18 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   io.redirect := DontCare //TODO
   io.redirect.valid := false.B //TODO
 
+  // debug info
+  XSDebug("head %d tail %d\n", ringBufferHead, ringBufferTail)
+  XSDebug("")
+  XSDebug(){
+    for(i <- 0 until RoqSize){
+      when(!valid(i)){printf("-")}
+      when(valid(i) && writebacked(i)){printf("w")}
+      when(valid(i) && !writebacked(i)){printf("v")}
+    }
+    printf("\n")
+  }
+
   //difftest signals
   val firstValidCommit = ringBufferTail + PriorityMux(validCommit, VecInit(List.tabulate(CommitWidth)(_.U)))
   val emptyCsr = WireInit(0.U(64.W))