Predecode: replace old PDecode

src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.decode.isa.predecode
 import chisel3.util._
 import xiangshan.frontend.BrType
 
-object PreDecode {
+object PreDecodeInst {
   def C_JAL     = BitPat("b????????????????_?01_?_??_???_??_???_01")  //c.jal & c.j  //C_ADDIW?
   def C_JALR    = BitPat("b????????????????_100_?_??_???_00_000_10")  //c.jalr & c.jr
   def C_BRANCH  = BitPat("b????????????????_11?_?_??_???_??_???_01")

src/main/scala/xiangshan/frontend/PDecode.scala

-package xiangshan.frontend
-
-import chisel3._
-import chisel3.util._
-import xiangshan._
-import utils._
-import xiangshan.backend.decode.isa.predecode.PreDecode
-
-object BrType {
-  def notBr   = "b00".U
-  def branch  = "b01".U
-  def jal     = "b10".U
-  def jalr    = "b11".U
-  def apply() = UInt(2.W)
-}
-
-object ExcType {  //TODO:add exctype
-  def notExc = "b000".U
-  def apply() = UInt(3.W)
-}
-
-class PreDecodeInfo extends XSBundle{  // 8 bit
-  val isRVC   = Bool()
-  val brType  = UInt(2.W)
-  val isCall  = Bool()
-  val isRet   = Bool()
-  val excType = UInt(3.W)
-  def isBr = brType === BrType.branch
-  def isJal = brType === BrType.jal
-  def isJalr = brType === BrType.jalr
-}
-
-class CacheLine extends XSBundle {
-  val cacheLine = Output(UInt(256.W))
-}
-
-//how to load predecode information?
-//use PC(6,1) to locate predecode information
-class PDecode extends XSModule {
-  val io = IO(new Bundle() {
-    val in = Input(Vec(FetchWidth,UInt(32.W)))
-    val out = Output(Vec(FetchWidth, new PreDecodeInfo))
-  })
-
-  //val catCacheLine = Cat(0.U(16.W),io.in.bits.cacheLine)    //TODO:add span two Cache-Line
-  val cacheInstr = io.in
-  // val preDecodeInfo = io.out
-
-  val preDecodeTemp = Reg(Vec(FetchWidth, new PreDecodeInfo))
-  val cacheLineTemp = Reg((new CacheLine).cacheLine)
-  val validLatch = RegInit(false.B)
-
-  def isRVC(instr: UInt) = instr(1,0) =/= "b11".U
-  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
-  def brInfo(instr: UInt) = {
-    val rd = instr(11,7)
-    val rs = instr(19,15)
-    val res::Nil = ListLookup(instr, List(BrType.notBr), PreDecode.brTable)
-    val isCall = (res === BrType.jal || res === BrType.jalr) && isLink(rd) && !isRVC(instr)
-    val isRet = res === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
-    List(res, isCall, isRet)
-  }
-
-  for(i <- 0 until FetchWidth) {
-    val brType::isCall::isRet::Nil = brInfo(cacheInstr(i))
-    io.out(i).isRVC  := isRVC(cacheInstr(i))
-    io.out(i).brType := brType
-    io.out(i).isCall := isCall
-    io.out(i).isRet  := isRet
-    io.out(i).excType := ExcType.notExc
-  }
-
-
-//  validLatch := io.in.valid
-//  io.preDecodeInfo.bits := preDecodeTemp
-//  io.preDecodeInfo.valid := validLatch
-//
-//  cacheLineTemp := io.in.bits.cacheLine
-//  io.out.valid := validLatch
-//  io.out.bits.cacheLine := cacheLineTemp
-
-//  XSDebug("cacheinstr:\n")
-//  for(i <- 0 until FetchWidth) {
-//    XSDebug(io.out.valid, p"${Binary(cacheInstr(i))}\n")
-//  }
-
-  for(i <- 0 until FetchWidth) {
-    XSDebug(//io.preDecodeInfo.valid,
-      p"instr ${Hexadecimal(cacheInstr(i))} " +
-      p"RVC = ${Binary(io.out(i).isRVC)}, " +
-      p"BrType = ${Binary(io.out(i).brType)}, " +
-      p"isCall = ${Binary(io.out(i).isCall)}, " +
-      p"isRet = ${Binary(io.out(i).isRet)} \n")
-  }
-}

src/main/scala/xiangshan/frontend/PreDecode.scala

+package xiangshan.frontend
+
+import chisel3._
+import chisel3.util._
+import xiangshan._
+import xiangshan.backend.decode.isa.predecode.PreDecodeInst
+
+trait HasPdconst{ this: XSModule =>
+  val halfWidth = FetchWidth * 2
+  val groupAlign = log2Up(FetchWidth * 4)
+  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
+  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
+  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
+  def brInfo(instr: UInt) = {
+    val rd = instr(11,7)
+    val rs = instr(19,15)
+    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
+    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
+    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
+    List(brType, isCall, isRet)
+  }
+}
+
+object BrType {
+  def notBr   = "b00".U
+  def branch  = "b01".U
+  def jal     = "b10".U
+  def jalr    = "b11".U
+  def apply() = UInt(2.W)
+
+}
+
+object ExcType {  //TODO:add exctype
+  def notExc = "b000".U
+  def apply() = UInt(3.W)
+}
+
+class PDInfo extends XSBundle{  // 8 bit
+  val isRVC   = Bool()
+  val brType  = UInt(2.W)
+  val isCall  = Bool()
+  val isRet   = Bool()
+  val excType = UInt(3.W)
+  def isBr = brType === BrType.branch
+  def isJal = brType === BrType.jal
+  def isJalr = brType === BrType.jalr
+}
+
+class PDPacket extends PDInfo{
+  val pc = UInt(VAddrBits.W)
+  val inst = UInt(32.W)
+  val mask = Bool()
+}
+
+class ICacheResp extends XSBundle {
+  val fetchPc = UInt(VAddrBits.W)
+  val data = UInt((FetchWidth * 32).W)
+  val mask = UInt((FetchWidth * 2).W)
+}
+
+class PreDecode extends XSModule with HasPdconst{
+  val io = IO(new Bundle() {
+    val in = Input(new ICacheResp)
+    val prevHalf = Input(UInt(16.W))
+    val prevValid = Input(false.B)
+
+    val out = Output(Vec(halfWidth, new PDPacket))
+  })
+
+  val gpc = groupPC(io.in.fetchPc)
+  val data = io.in.data
+  val mask = io.in.mask
+
+  val insts = Wire(Vec(halfWidth, UInt(32.W)))
+  val instsMask = Wire(Vec(halfWidth, Bool()))
+  val instsRVC = Wire(Vec(halfWidth,Bool()))
+  val instsPC = Wire(Vec(halfWidth, UInt(VAddrBits.W)))
+  val nextHalf = Wire(UInt(16.W))
+
+  for (i <- 0 until halfWidth) {
+    val inst = Wire(UInt(32.W))
+    val valid = Wire(Bool())
+    val pc = gpc + (i << 1).U - Mux(io.prevValid && (i.U === 0.U), 2.U, 0.U)
+
+    if (i==0) {
+      inst := Mux(io.prevValid, Cat(data(15,0), io.prevHalf), data(31,0))
+      valid := true.B
+    } else if (i==1) {
+      inst := data(47,16)
+      valid := io.prevValid || !(instsMask(0) && !isRVC(insts(0)))
+    } else if (i==halfWidth-1) {
+      inst := Cat(0.U(16.W), data(i*16+15, i*16))
+      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
+    } else {
+      inst := data(i*16+31, i*16)
+      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
+    }
+
+    insts(i) := inst
+    instsRVC(i) := isRVC(inst)
+    instsMask(i) := mask(i) && valid
+    instsPC(i) := pc
+
+    val brType::isCall::isRet::Nil = brInfo(inst)
+    io.out(i).isRVC := instsRVC(i)
+    io.out(i).brType := brType
+    io.out(i).isCall := isCall
+    io.out(i).isRet := isRet
+    io.out(i).excType := ExcType.notExc
+    io.out(i).inst := insts(i)
+    io.out(i).mask := instsMask(i)
+    io.out(i).pc := instsPC(i)
+  }
+
+
+//  for (i <- 0 until halfWidth) {
+//    XSDebug(true.B,
+//      p"instr ${Binary(io.out(i).inst)}, " +
+//        p"mask ${Binary(io.out(i).mask)}, " +
+//        //p"pc ${Binary(io.out(i).pc)}, " +
+//        p"isRVC ${Binary(io.out(i).isRVC)}, " +
+//        p"brType ${Binary(io.out(i).brType)}, " +
+//        p"isRet ${Binary(io.out(i).isRet)}, " +
+//        p"isCall ${Binary(io.out(i).isCall)}\n"
+//    )
+//  }
+}
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