LoadUnit: support flw

src/main/scala/xiangshan/XSCore.scala

@@ -28,7 +28,7 @@ case class XSCoreParameters
   AddrBits: Int = 64,
   VAddrBits: Int = 39,
   PAddrBits: Int = 40,
-  HasFPU: Boolean = false,
+  HasFPU: Boolean = true,
   FectchWidth: Int = 8,
   EnableBPU: Boolean = true,
   EnableBPD: Boolean = true,
@@ -72,9 +72,9 @@ case class XSCoreParameters
     AluCnt = 4,
     MulCnt = 0,
     MduCnt = 2,
-    FmacCnt = 4,
-    FmiscCnt = 1,
-    FmiscDivSqrtCnt = 1,
+    FmacCnt = 0,
+    FmiscCnt = 0,
+    FmiscDivSqrtCnt = 0,
     LduCnt = 2,
     StuCnt = 2
   ),

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -6,6 +6,7 @@ import utils._
 import xiangshan._
 import xiangshan.cache.{DCacheLoadIO, TlbRequestIO, TlbCmd, MemoryOpConstants}
 import xiangshan.backend.LSUOpType
+import xiangshan.backend.fu.fpu.boxF32ToF64
 
 class LoadToLsroqIO extends XSBundle {
   val loadIn = ValidIO(new LsPipelineBundle)
@@ -265,7 +266,8 @@ class LoadUnit extends XSModule {
       LSUOpType.ld   -> SignExt(rdataSel(63, 0), XLEN),
       LSUOpType.lbu  -> ZeroExt(rdataSel(7, 0) , XLEN),
       LSUOpType.lhu  -> ZeroExt(rdataSel(15, 0), XLEN),
-      LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN)
+      LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN),
+      LSUOpType.flw  -> boxF32ToF64(rdataSel(31, 0))
   ))
 
   // ecc check