Merge remote-tracking branch 'origin/temp-lsu-test' into dev-new-dispatch

src/main/scala/xiangshan/backend/Backend.scala

@@ -12,7 +12,7 @@ import xiangshan.backend.brq.Brq
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
 import xiangshan.backend.fu.FunctionUnit
-import xiangshan.backend.issue.{IssueQueue, RegfileReader, ReservedStation}
+import xiangshan.backend.issue.{IssueQueue, ReservationStation}
 import xiangshan.backend.regfile.{Regfile, RfWritePort}
 import xiangshan.backend.roq.Roq
 import xiangshan.mem._
@@ -102,7 +102,7 @@ class Backend(implicit val p: XSConfig) extends XSModule
 
       println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt")
 
-      val rs = Module(new ReservedStation(
+      val rs = Module(new ReservationStation(
         cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, false
       ))
       rs.io.redirect <> redirect
@@ -160,13 +160,9 @@ class Backend(implicit val p: XSConfig) extends XSModule
       iq
     })
 
-  val rfReader = Module(new RegfileReader(memConfigs, exeWbReqs.length))
-  rfReader.io.in <> issueQueues.map(_.io.deq)
-  rfReader.io.bypasses <> exeWbReqs
-
   io.mem.mcommit := roq.io.mcommit
-  io.mem.ldin <> rfReader.io.out.take(exuParameters.LduCnt)
-  io.mem.stin <> rfReader.io.out.takeRight(exuParameters.StuCnt)
+  io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
+  io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
   jmpExeUnit.io.exception.valid := roq.io.redirect.valid
   jmpExeUnit.io.exception.bits := roq.io.exception
 
@@ -188,10 +184,10 @@ class Backend(implicit val p: XSConfig) extends XSModule
   rename.io.redirect <> redirect
   rename.io.roqCommits <> roq.io.commits
   rename.io.in <> decBuf.io.out
-  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ issueQueues.flatMap(_.io.intRfReadAddr)
-  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ issueQueues.flatMap(_.io.intSrcRdy)
-  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ issueQueues.flatMap(_.io.fpRfReadAddr)
-  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ issueQueues.flatMap(_.io.fpSrcRdy)
+  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr
+  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
+  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr
+  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
   dispatch.io.redirect <> redirect
   dispatch.io.fromRename <> rename.io.out
 
@@ -202,8 +198,8 @@ class Backend(implicit val p: XSConfig) extends XSModule
   dispatch.io.moqIdxs <> io.mem.moqIdxs
 
   intRf.io.readPorts <> dispatch.io.readIntRf
-  fpRf.io.readPorts <> dispatch.io.readFpRf ++ rfReader.io.readFpRf
-  memRf.io.readPorts <> rfReader.io.readIntRf
+  fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf)
+  memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf)
 
   val wbIntIdx = exuConfigs.zipWithIndex.filter(_._1.writeIntRf).map(_._2)
   val wbFpIdx = exuConfigs.zipWithIndex.filter(_._1.writeFpRf).map(_._2)

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -20,12 +20,19 @@ class Dispatch(exuCfg: Array[ExuConfig]) extends XSModule with NeedImpl {
     val toMoq =  Vec(RenameWidth, DecoupledIO(new MicroOp))
     // get MoqIdx
     val moqIdxs = Input(Vec(RenameWidth, UInt(MoqIdxWidth.W)))
+
     // read regfile
     val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
     val readFpRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new RfReadPort))
     // read reg status (busy/ready)
     val intPregRdy = Vec(NRIntReadPorts, Input(Bool()))
     val fpPregRdy = Vec(NRFpReadPorts - exuParameters.StuCnt, Input(Bool()))
+    // load + store reg status (busy/ready)
+    val intMemRegAddr = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    val fpMemRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
+    val intMemRegRdy = Vec(NRMemReadPorts, Input(Bool()))
+    val fpMemRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
+
     // to reservation stations
     val numExist = Input(Vec(exuParameters.ExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.ExuCnt, DecoupledIO(new MicroOp))

src/main/scala/xiangshan/backend/issue/ReservedStation.scala → src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -34,10 +34,8 @@ class IssueQueue
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
     val enq = Flipped(DecoupledIO(new MicroOp))
-    val intRfReadAddr = Output(Vec(exuCfg.intSrcCnt, UInt(PhyRegIdxWidth.W)))
-    val intSrcRdy = Input(Vec(exuCfg.intSrcCnt, Bool()))
-    val fpRfReadAddr = Output(Vec(exuCfg.fpSrcCnt, UInt(PhyRegIdxWidth.W)))
-    val fpSrcRdy = Input(Vec(exuCfg.fpSrcCnt, Bool()))
+    val readIntRf = Vec(exuCfg.intSrcCnt, Flipped(new RfReadPort))
+    val readFpRf = Vec(exuCfg.fpSrcCnt, Flipped(new RfReadPort))
     val deq = DecoupledIO(new ExuInput)
     val wakeUpPorts = Vec(wakeupCnt, Flipped(ValidIO(new ExuOutput)))
     val bypassUops = Vec(bypassCnt, Flipped(ValidIO(new MicroOp)))
@@ -45,22 +43,7 @@ class IssueQueue
   })
 }
 
-class RegfileReader(cfgs: Seq[ExuConfig], bypassCnt: Int) extends Module with NeedImpl {
-
-  val numIntRfRead = cfgs.map(_.intSrcCnt).sum
-  val numFpRfRead = cfgs.map(_.fpSrcCnt).sum
-
-  val io = IO(new Bundle() {
-    // from issue queue
-    val in = Vec(cfgs.length, Flipped(DecoupledIO(new ExuInput)))
-    val bypasses = Vec(bypassCnt, Flipped(DecoupledIO(new ExuOutput)))
-    val readIntRf = Vec(numIntRfRead, Flipped(new RfReadPort))
-    val readFpRf = Vec(numFpRfRead, Flipped(new RfReadPort))
-    val out = Vec(cfgs.length, DecoupledIO(new ExuInput))
-  })
-}
-
-class ReservedStation
+class ReservationStation
 (
   val exuCfg: ExuConfig,
   val wakeupCnt: Int,

src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala

@@ -18,7 +18,7 @@ class IssueQueueTest extends FlatSpec
 {
   XSLog.generateLog = false
   it should "do enq issue with no delay correctly" in {
-    test(new ReservedStation(Exu.aluExeUnitCfg, wakeupCnt = 1, bypassCnt = 1, fifo = false) {
+    test(new ReservationStation(Exu.aluExeUnitCfg, wakeupCnt = 1, bypassCnt = 1, fifo = false) {
       AddSinks()
     }) { c =>