[WIP]v2backend: add backend parameters

src/main/scala/xiangshan/v2backend/BackendParams.scala

+package xiangshan.v2backend
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3._
+import chisel3.util._
+import xiangshan.v2backend.issue.IssueQueueParams
+import xiangshan.{FuType, XSCoreParamsKey}
+
+object SchdBlockParams {
+  def dummyIntParams(numDeqOutside: Int = 0)(implicit p: Parameters): SchdBlockParams = {
+    implicit val schdType: IntScheduler = IntScheduler()
+    val numUopIn = 6
+    val numRfRead = 14
+    val numRfWrite = 8
+    val numPregs = 160
+    val params = SchdBlockParams(Seq(
+      IssueBlockParams(Seq(
+        ExuBlockParams(Seq(AluCfg, VsetCfg, CsrCfg, FenceCfg, MulCfg, BkuCfg)),
+        ExuBlockParams(Seq(AluCfg, MulCfg, BkuCfg)),
+      ), numEntries = 16, pregBits = numPregs, numWakeupFromWB = numRfWrite, numEnq = 4),
+      IssueBlockParams(Seq(
+        ExuBlockParams(Seq(AluCfg, DivCfg, I2fCfg)),
+        ExuBlockParams(Seq(AluCfg, DivCfg)),
+      ), numEntries = 16, pregBits = numPregs, numWakeupFromWB = numRfWrite, numEnq = 4),
+      IssueBlockParams(Seq(
+        ExuBlockParams(Seq(BrhCfg, JmpCfg)),
+        ExuBlockParams(Seq(BrhCfg))
+      ), numEntries = 16, pregBits = numPregs, numWakeupFromWB = numRfWrite, numEnq = 4),
+    ),
+      numPregs = numPregs,
+      numRfReadWrite = Some((numRfRead, numRfWrite)),
+      numDeqOutside = numDeqOutside,
+      schdType = schdType,
+      rfDataWidth = p(XSCoreParamsKey).XLEN,
+      numUopIn = numUopIn
+    )
+    params
+  }
+}
+
+case class SchdBlockParams(
+  issueBlockParams: Seq[IssueBlockParams],
+  numPregs        : Int,
+  numRfReadWrite  : Option[(Int, Int)],
+  numDeqOutside   : Int,
+  schdType        : SchedulerType,
+  rfDataWidth     : Int,
+  numUopIn        : Int,
+) {
+  def JmpCnt      :Int = issueBlockParams.map(_.JmpCnt).sum
+  def BrhCnt      :Int = issueBlockParams.map(_.BrhCnt).sum
+  def I2fCnt      :Int = issueBlockParams.map(_.I2fCnt).sum
+  def CsrCnt      :Int = issueBlockParams.map(_.CsrCnt).sum
+  def AluCnt      :Int = issueBlockParams.map(_.AluCnt).sum
+  def MulCnt      :Int = issueBlockParams.map(_.MulCnt).sum
+  def DivCnt      :Int = issueBlockParams.map(_.DivCnt).sum
+  def FenceCnt    :Int = issueBlockParams.map(_.FenceCnt).sum
+  def BkuCnt      :Int = issueBlockParams.map(_.BkuCnt).sum
+  def VsetCnt     :Int = issueBlockParams.map(_.VsetCnt).sum
+
+  def FmacCnt     :Int = issueBlockParams.map(_.FmacCnt).sum
+  def FmiscCnt    :Int = issueBlockParams.map(_.FmiscCnt).sum
+  def fDivSqrtCnt :Int = issueBlockParams.map(_.fDivSqrtCnt).sum
+
+  def LduCnt      :Int = issueBlockParams.map(_.LduCnt).sum
+  def StuCnt      :Int = issueBlockParams.map(_.StuCnt).sum
+  def MouCnt      :Int = issueBlockParams.map(_.MouCnt).sum
+
+  def VipuCnt     :Int = issueBlockParams.map(_.VipuCnt).sum
+  def VfpuCnt     :Int = issueBlockParams.map(_.VfpuCnt).sum
+  def VlduCnt     :Int = issueBlockParams.map(_.VlduCnt).sum
+  def VstuCnt     :Int = issueBlockParams.map(_.VstuCnt).sum
+
+  def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum
+  def numWriteFpRf : Int = issueBlockParams.map(_.numWriteFpRf ).sum
+  def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum
+}
+
+case class IssueBlockParams(
+  // top down
+  exuBlockParams     : Seq[ExuBlockParams],
+  numEntries         : Int,
+  pregBits           : Int,
+  numWakeupFromWB    : Int,
+  numDeqOutside      : Int = 0,
+  numWakeupFromOthers: Int = 0,
+  // calculate in scheduler
+  var numEnq         : Int = 0,
+  var numWakeupFromIQ: Int = 0,
+)(implicit
+  // top down
+  val schdType       : SchedulerType,
+  val p              : Parameters,
+) {
+  def numIntSrc     : Int = exuBlockParams.map(_.numIntSrc).max
+  def numFpSrc      : Int = exuBlockParams.map(_.numFpSrc ).max
+  def numVecSrc     : Int = exuBlockParams.map(_.numVecSrc).max
+  def readIntRf     : Boolean = numIntSrc > 0
+  def readFpRf      : Boolean = numFpSrc  > 0
+  def readVecRf     : Boolean = numVecSrc > 0
+  def writeIntRf    : Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _)
+  def writeFpRf     : Boolean = exuBlockParams.map(_.writeFpRf ).reduce(_ || _)
+  def writeVecRf    : Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _)
+  def exceptionOut  : Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted
+  def hasLoadError  : Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _)
+  def flushPipe     : Boolean = exuBlockParams.map(_.flushPipe).reduce(_ ||_)
+  def replayInst    : Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _)
+  def trigger       : Boolean = exuBlockParams.map(_.trigger).reduce(_ || _)
+  def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger
+
+  def numWriteIntRf : Int = exuBlockParams.count(_.writeIntRf)
+  def numWriteFpRf  : Int = exuBlockParams.count(_.writeFpRf)
+  def numWriteVecRf : Int = exuBlockParams.count(_.writeVecRf)
+
+  def numRegSrcMax  : Int = numIntSrc max numFpSrc max numVecSrc
+  def dataBitsMax   : Int = if (numVecSrc > 0) p(XSCoreParamsKey).VLEN else p(XSCoreParamsKey).XLEN
+  def numDeq        : Int = numDeqOutside + exuBlockParams.length
+
+  def JmpCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum
+  def BrhCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum
+  def I2fCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum
+  def CsrCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum
+  def AluCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum
+  def MulCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum
+  def DivCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum
+  def FenceCnt    :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum
+  def BkuCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum
+  def VsetCnt     :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vset)).sum
+
+  def FmacCnt     :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum
+  def FmiscCnt    :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum
+  def fDivSqrtCnt :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum
+
+  def LduCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.ldu)).sum
+  def StuCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.stu)).sum
+  def MouCnt      :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum
+
+  def VipuCnt     :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum
+  def VfpuCnt     :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum
+  def VlduCnt     :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum
+  def VstuCnt     :Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum
+
+  def getWbParams: Seq[Seq[WriteBackConfig]] = exuBlockParams.map(params => params.getWbParamsOuter)
+
+  def generateIqParams: IssueQueueParams = {
+    IssueQueueParams(
+      numEntries = numEntries,
+      numEnq = numEnq,
+      numDeq = numDeq,
+      numSrc = numRegSrcMax,
+      dataBits = dataBitsMax,
+      pregBits = pregBits,
+      numWakeupFromWB = numWakeupFromWB,
+      schdType = schdType,
+      numWakeupFromIQ = numWakeupFromIQ,
+      numWakeupFromOthers = numWakeupFromOthers,
+      hasBranch = BrhCnt > 0,
+      hasJump = JmpCnt > 0,
+      hasLoad = LduCnt > 0,
+      hasStore = StuCnt > 0,
+      hasMemAddr = LduCnt > 0 || StuCnt > 0
+    )
+  }
+
+  def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct
+}
+
+case class ExuBlockParams(
+  fuConfigs: Seq[FuConfig],
+)(implicit val schdType: SchedulerType) {
+  val numIntSrc     : Int = fuConfigs.map(_.numIntSrc).max
+  val numFpSrc      : Int = fuConfigs.map(_.numFpSrc ).max
+  val numVecSrc     : Int = fuConfigs.map(_.numVecSrc).max
+  val readIntRf     : Boolean = numIntSrc > 0
+  val readFpRf      : Boolean = numFpSrc  > 0
+  val readVecRf     : Boolean = numVecSrc > 0
+  val writeIntRf    : Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _)
+  val writeFpRf     : Boolean = fuConfigs.map(_.writeFpRf ).reduce(_ || _)
+  val writeVecRf    : Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _)
+  val writeFflags   : Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _)
+  val hasRedirect   : Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _)
+  val exceptionOut  : Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted
+  val hasLoadError  : Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _)
+  val flushPipe     : Boolean = fuConfigs.map(_.flushPipe).reduce(_ ||_)
+  val replayInst    : Boolean = fuConfigs.map(_.replayInst).reduce(_ || _)
+  val trigger       : Boolean = fuConfigs.map(_.trigger).reduce(_ || _)
+  val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger
+
+  def getWBSource: SchedulerType = {
+    schdType
+  }
+
+  def hasCrossWb: Boolean = {
+    schdType match {
+      case IntScheduler() => writeFpRf || writeVecRf
+      case VfScheduler() => writeIntRf
+      case _ => false
+    }
+  }
+
+  def canAccept(fuType: UInt): Bool = {
+    Cat(fuConfigs.map(_.fuType === fuType)).orR
+  }
+
+  def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _)
+
+  def getWbParamsInner: Seq[Seq[WriteBackConfig]] = {
+    this.fuConfigs.map(cfg => {
+      val res = Seq()
+      if (cfg.writeIntRf) res :+ WriteBackConfig(getWBSource, IntScheduler())
+      if (cfg.writeFpRf)  res :+ WriteBackConfig(getWBSource, VfScheduler())
+      if (cfg.writeVecRf) res :+ WriteBackConfig(getWBSource, VfScheduler())
+      res
+    })
+  }
+
+  def getWbParamsOuter: Seq[WriteBackConfig] = {
+    val res = Seq()
+    if (writeIntRf) res :+ WriteBackConfig(getWBSource, IntScheduler())
+    if (writeFpRf || writeVecRf) res :+ WriteBackConfig(getWBSource, VfScheduler())
+    res
+  }
+}
+
+
+

src/main/scala/xiangshan/v2backend/Scheduler.scala

+package xiangshan.v2backend
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import xiangshan.backend.regfile.{IntRegFile, VfRegFile}
+import xiangshan.backend.rename.{BusyTable, BusyTableReadIO}
+import xiangshan.v2backend.Bundles.{DynInst, ExuInput, ExuOutput}
+import xiangshan.{HasXSParameter, Redirect, ResetPregStateReq, XSBundle}
+import xiangshan.v2backend.issue._
+import xiangshan.FuType
+
+sealed trait SchedulerType
+
+case class IntScheduler() extends SchedulerType
+case class MemScheduler() extends SchedulerType
+case class VfScheduler() extends SchedulerType
+case class NoScheduler() extends SchedulerType
+
+class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
+
+  lazy val module = new SchedulerImp(this)(params, p)
+}
+
+class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle {
+  val fromTop = new Bundle {
+    val hartId = Input(UInt(8.W))
+  }
+  val fromRob = new Bundle {
+    val flush = Flipped(ValidIO(new Redirect))
+  }
+  val fromDispatch = new Bundle {
+    val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq))
+    val uops =  Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst)))
+  }
+  val writeback = MixedVec(
+    Vec(params.issueBlockParams.map(_.getWbParams).count { case WBFromInt() | WBFromMem() => true }, new ExuOutput(XLEN)),
+    Vec(params.issueBlockParams.map(_.getWbParams).count { case WBFromVec() => true }, new ExuOutput(VLEN)),
+    Vec(params.issueBlockParams.map(_.getWbParams).count { case WBFromFp() => true }, new ExuOutput(VLEN)),
+  )
+  val toDataPath = new Bundle {
+    val exuInput: MixedVec[DecoupledIO[ExuInput]] = MixedVec(
+      params.iqConfigs.map(_.generateIssueBundle)
+    )
+    val rfRead = MixedVec(
+      params.iqConfigs.map(_.generateReadRfBundle)
+    )
+  }
+}
+
+class SchedulerImp(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters)
+  extends LazyModuleImp(wrapper)
+    with HasXSParameter
+{
+  val io = IO(new SchedulerIO())
+
+  // alias
+  private val schdType = params.schdType
+  private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0))
+  private val numPregs = params.numPregs
+
+  // Modules
+  private val splitNum = schdType match {
+    case VfScheduler() => VLEN / XLEN
+    case _ => 1
+  }
+
+  private val rfRaddr = Wire(Vec(numRfRead, UInt(VAddrBits.W)))
+  private val rfRdata = Wire(Vec(numRfRead, UInt(params.rfDataWidth.W)))
+  private val rfWen = Wire(Vec(splitNum, Vec(numRfWrite, Bool())))
+  private val rfWaddr = Wire(Vec(numRfWrite, UInt(VAddrBits.W)))
+  private val rfWdata = Wire(Vec(numRfWrite, UInt(params.rfDataWidth.W)))
+
+  // RegFile Modules
+  schdType match {
+    case IntScheduler() => IntRegFile("IntRegFile", numPregs, rfRaddr, rfRdata, rfWen(0), rfWaddr, rfWdata)
+    case VfScheduler() => VfRegFile("VfRegFile", numPregs, splitNum, rfRaddr, rfRdata, rfWen, rfWaddr, rfWdata)
+    case MemScheduler() => _
+  }
+
+  // BusyTable Modules
+  val intBusyTable = schdType match {
+    case IntScheduler() => Some(Module(new BusyTable(intBusyTableRead.get.length, intBusyTableWb.get.length)))
+    case _ => None
+  }
+
+  val vfBusyTable = schdType match {
+    case VfScheduler() => Some(Module(new BusyTable(vfBusyTableRead.get.length, vfBusyTableWb.get.length)))
+    case _ => None
+  }
+
+  val issueQueueWrappers = wrapper.params.iqConfigs.map(x => LazyModule(new IssueQueue(x)))
+  val issueQueues = issueQueueWrappers.map(_.module)
+
+  private val (intBusyTableRead, intBusyTableWb) = schdType match {
+    case IntScheduler() => (
+      Some(Vec(params.numRegFileReadPorts, new BusyTableReadIO)),
+      Some(Vec(numRfWrite, ValidIO(UInt(params.pregIdxWidth.W))))
+    )
+    case _ => (None, None)
+  }
+
+  private val (vfBusyTableRead, vfBusyTableWb) = schdType match {
+    case VfScheduler() => (
+      Some(Vec(params.numRegFileReadPorts, new BusyTableReadIO)),
+      Some(Vec(numRfWrite, ValidIO(UInt(params.pregIdxWidth.W))))
+    )
+    case _ => (None, None)
+  }
+
+  intBusyTable match {
+    case Some(bt) =>
+      bt.io.read <> intBusyTableRead.get
+      bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) =>
+        btAllocPregs.valid := dpAllocPregs.isInt
+        btAllocPregs.bits := dpAllocPregs.preg
+      }
+      bt.io.wbPregs <> intBusyTableWb.get
+    case None =>
+  }
+
+  vfBusyTable match {
+    case Some(bt) =>
+      bt.io.read <> vfBusyTableRead.get
+      bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) =>
+        btAllocPregs.valid := dpAllocPregs.isFp
+        btAllocPregs.bits := dpAllocPregs.preg
+      }
+      bt.io.wbPregs <> vfBusyTableWb.get
+    case None =>
+  }
+
+  issueQueues.zipWithIndex.foreach { case (iq, i) =>
+    iq.io.flush <> io.fromRob.flush
+    iq.io.enq.zip(io.fromDispatch.uops).foreach { case (iqEnq, dpUop) =>
+      iqEnq.valid := s1
+
+    }
+  }
+
+  // valid singals need initialize, while uop data need not
+  val s1_uopsValid: Vec[Bool] = RegInit(VecInit(Seq.fill(params.numUopIn)(false.B)))
+  val s1_uopsVec = Reg(Vec(params.numUopIn, new DynInst))
+
+  val uopsInFired = io.fromDispatch.uops.map(_.fire)
+  val uopsOutFired = io.toDataPath.exuInput.zip(io.toDataPath.rfRead).map{ case (exuInput, rfRead) => exuInput.fire && rfRead.fire}
+
+
+
+  s1_uopsValid.zipWithIndex.foreach { case (valid, i) =>
+    when (io.fromRob.flush.valid) {
+      valid := false.B
+    }.elsewhen(uopsOutFired(i)) {
+      valid := uopsInFired(i)
+    }
+  }
+
+  s1_uopsVec.zipWithIndex.foreach { case (uop, i) =>
+    when (!io.fromRob.flush.valid) {
+      when (uopsInFired(i) && (uopsOutFired(i) || !s1_uopsValid(i))) {
+        uop := io.fromDispatch.uops(i)
+      }
+    }
+  }
+
+
+}

src/main/scala/xiangshan/v2backend/issue/IssueQueue.scala

@@ -5,22 +5,19 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import xiangshan.mem.{MemWaitUpdateReq, SqPtr}
-import xiangshan.v2backend.Bundles.{DynInst, ExuInput, WriteBackBundle, IssueQueueWakeUpBundle}
+import xiangshan.v2backend.Bundles.{DynInst, ExuInput, IssueQueueWakeUpBundle, WriteBackBundle}
+import xiangshan.v2backend._
 import xiangshan.{HasXSParameter, MemRSFeedbackIO, Redirect, XSBundle}
 
-trait Region
-case class IntRegion() extends Region
-case class VfRegion() extends Region
-
 case class IssueQueueParams(
-  region                 : Region,
-  var numEntries         : Int = 0,
-  var numEnq             : Int = 0,
-  var numDeq             : Int = 0,
-  var numSrc             : Int = 0,
-  var dataBits           : Int = 0,
-  var pregBits           : Int = 0,
-  var numWakeupFromWB    : Int = 0,
+  var numEntries         : Int,
+  var numEnq             : Int,
+  var numDeq             : Int,
+  var numSrc             : Int,
+  var dataBits           : Int,
+  var pregBits           : Int,
+  var numWakeupFromWB    : Int,
+  var schdType           : SchedulerType = NoScheduler(),
   var numWakeupFromIQ    : Int = 0,
   var numWakeupFromOthers: Int = 0,
   var hasBranch          : Boolean = false,
@@ -35,12 +32,20 @@ case class IssueQueueParams(
   def hasLoadStore = hasLoad || hasStore || hasMemAddr
   def hasRedirectOut = hasBranch || hasJump
   def numAllWakeup: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers
+
+  def generateIssueBundle: DecoupledIO[ExuInput] = {
+    DecoupledIO(new ExuInput(this.dataBits, this.numSrc))
+  }
+
+  def generateReadRfBundle: DecoupledIO[UInt] = {
+    DecoupledIO(UInt(this.pregBits.W))
+  }
 }
 
 object DummyIQParams {
   def apply(): IssueQueueParams = {
     IssueQueueParams(
-      region           = IntRegion(),
+      schdType         = IntScheduler(),
       numEntries       = 16,
       numEnq           = 2,
       numDeq           = 2,
@@ -52,12 +57,12 @@ object DummyIQParams {
   }
 }
 
-class IssueQueue(implicit p: Parameters) extends LazyModule {
-  implicit val iqParams = DummyIQParams() // Todo: initialize it
+class IssueQueue(params: IssueQueueParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
+  implicit val iqParams = params
 
-  lazy val module = iqParams.region match {
-    case IntRegion() => new IssueQueueIntImp(this)
-    case VfRegion() => new IssueQueueImp(this)
+  lazy val module = iqParams.schdType match {
+    case IntScheduler() => new IssueQueueIntImp(this)
+    case _ => new IssueQueueImp(this)
   }
 }
 

src/main/scala/xiangshan/v2backend/issue/StatusArray.scala

@@ -4,10 +4,10 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import utils.XSError
-import xiangshan._
 import xiangshan.backend.rob.RobPtr
 import xiangshan.mem.SqPtr
 import xiangshan.v2backend.Bundles.IssueQueueWakeUpBundle
+import xiangshan._
 
 class StatusEntry(implicit p:Parameters, params: IssueQueueParams) extends Bundle {
   val srcState = Vec(params.numSrc, SrcState())

src/main/scala/xiangshan/v2backend/package.scala

+package xiangshan
+
+import chisel3.UInt
+import xiangshan.ExceptionNO._
+import xiangshan.backend.fu.{CertainLatency, HasFuLatency, UncertainLatency}
+
+// Todo: split it into other config files
+package object v2backend {
+  sealed trait WBSource
+  case class WBFromInt() extends WBSource
+  case class WBFromMem() extends WBSource
+  case class WBFromVec() extends WBSource
+  case class WBFromFp()  extends WBSource
+
+  sealed trait WBSink
+  case class WBToInt() extends WBSink
+  case class WBToFp()  extends WBSink
+  case class WBToVec() extends WBSink
+
+  case class WriteBackConfig(
+    wbSource: SchedulerType,
+    wbSink: SchedulerType,
+  ) {
+
+  }
+
+  case class FuConfig (
+    fuType: UInt,
+    numIntSrc: Int,
+    numFpSrc: Int,
+    numVecSrc: Int = 0,
+    writeIntRf: Boolean,
+    writeFpRf: Boolean,
+    writeVecRf: Boolean = false,
+    writeFflags: Boolean = false,
+    dataBits: Int = 64,
+    hasRedirect: Boolean = false,
+    latency: HasFuLatency = CertainLatency(0),
+    hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false),
+    exceptionOut: Seq[Int] = Seq(),
+    hasLoadError: Boolean = false,
+    flushPipe: Boolean = false,
+    replayInst: Boolean = false,
+    trigger: Boolean = false,
+  )
+
+  def JmpCfg: FuConfig = FuConfig (
+    fuType = FuType.jmp,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = true,
+    writeFpRf = false,
+    hasRedirect = true,
+  )
+
+  def BrhCfg = FuConfig (
+    fuType = FuType.brh,
+    numIntSrc = 2,
+    numFpSrc = 0,
+    writeIntRf = false,
+    writeFpRf = false,
+    hasRedirect = true,
+  )
+
+  def I2fCfg = FuConfig (
+    FuType.i2f,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = false,
+    writeFpRf = true,
+    writeFflags = true,
+    latency = CertainLatency(2),
+  )
+
+  def CsrCfg = FuConfig (
+    fuType = FuType.csr,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = true,
+    writeFpRf = false,
+    exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM),
+    flushPipe = true
+  )
+
+  def AluCfg: FuConfig = FuConfig (
+    fuType = FuType.alu,
+    numIntSrc = 2,
+    numFpSrc = 0,
+    writeIntRf = true,
+    writeFpRf = false,
+  )
+
+  def MulCfg = FuConfig (
+    FuType.mul,
+    2,
+    0,
+    writeIntRf = true,
+    writeFpRf = false,
+    latency = CertainLatency(2),
+  )
+
+  def DivCfg = FuConfig (
+    FuType.div,
+    2,
+    0,
+    writeIntRf = true,
+    writeFpRf = false,
+    latency = UncertainLatency(),
+    hasInputBuffer = (true, 4, true)
+  )
+
+  def FenceCfg: FuConfig = FuConfig (
+    FuType.fence,
+    numIntSrc = 2,
+    numFpSrc = 0,
+    writeIntRf = false,
+    writeFpRf = false,
+    latency = UncertainLatency(),
+    exceptionOut = Seq(illegalInstr),
+    flushPipe = true
+  )
+
+  // Todo: split it to simple bitmap exu and complex bku
+  def BkuCfg = FuConfig (
+    fuType = FuType.bku,
+    numIntSrc = 2,
+    numFpSrc = 0,
+    writeIntRf = true,
+    writeFpRf = false,
+    latency = CertainLatency(1),
+  )
+
+  def VsetCfg = FuConfig (
+    fuType = FuType.vset,
+    numIntSrc = 2,
+    numFpSrc = 0,
+    writeIntRf = true,
+    writeFpRf = false,
+    latency = CertainLatency(0)
+  )
+
+  def FmacCfg = FuConfig (
+    fuType = FuType.fmac,
+    numIntSrc = 0,
+    numFpSrc = 3,
+    writeIntRf = false,
+    writeFpRf = true,
+    writeFflags = true,
+    latency = UncertainLatency(),
+  )
+
+  def F2iCfg = FuConfig (
+    fuType = FuType.fmisc,
+    numIntSrc = 0,
+    numFpSrc = 1,
+    writeIntRf = true,
+    writeFpRf = false,
+    writeFflags = true,
+    latency = CertainLatency(2),
+  )
+
+  def F2fCfg = FuConfig (
+    fuType = FuType.fDivSqrt,
+    numIntSrc = 0,
+    numFpSrc = 2,
+    writeIntRf = false,
+    writeFpRf = true,
+    writeFflags = true,
+    latency = UncertainLatency(),
+    hasInputBuffer = (true, 8, true)
+  )
+
+  def FDivSqrtCfg = FuConfig (
+    fuType = FuType.fDivSqrt,
+    numIntSrc = 0,
+    numFpSrc = 2,
+    writeIntRf = false,
+    writeFpRf = true,
+    writeFflags = true,
+    latency = UncertainLatency(),
+    hasInputBuffer = (true, 8, true)
+  )
+
+  def LduCfg = FuConfig (
+    fuType = FuType.ldu,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = true,
+    writeFpRf = true,
+    latency = UncertainLatency(),
+    exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault),
+    flushPipe = true,
+    replayInst = true,
+    hasLoadError = true
+  )
+
+  def StaCfg = FuConfig (
+    fuType = FuType.stu,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = false,
+    writeFpRf = false,
+    latency = UncertainLatency(),
+    exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault)
+  )
+
+  def StdCfg = FuConfig (
+    fuType = FuType.stu,
+    numIntSrc = 1,
+    numFpSrc = 1,
+    writeIntRf = false,
+    writeFpRf = false,
+    latency = CertainLatency(1),
+    exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault)
+  )
+
+  def MouCfg = FuConfig (
+    fuType = FuType.mou,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = false,
+    writeFpRf = false,
+    latency = UncertainLatency(),
+    exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct
+  )
+
+  def MoudCfg = FuConfig (
+    fuType = FuType.mou,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    writeIntRf = false,
+    writeFpRf = false,
+    latency = UncertainLatency()
+  )
+
+  def VipuCfg = FuConfig (
+    fuType = FuType.vipu,
+    numIntSrc = 1,
+    numFpSrc = 0,
+    numVecSrc = 4,
+    writeIntRf = true,
+    writeFpRf = false,
+    writeVecRf = true,
+    latency = UncertainLatency(),
+  )
+
+  def VfpuCfg = FuConfig (
+    fuType = FuType.vfpu,
+    numIntSrc = 0,
+    numFpSrc = 1,
+    numVecSrc = 4,
+    writeIntRf = true,
+    writeFpRf = false,
+    writeVecRf = true,
+    latency = UncertainLatency(),
+  )
+  // Todo
+  // def VlduCfg = FuConfig ()
+  // def VstuCfg = FuConfig ()
+}

src/test/scala/xiangshan/v2backend/issue/IssueQueueMain.scala

@@ -10,6 +10,7 @@ object IssueQueueMain extends App {
     val (_, firrtlOpts, firrtlComplier) = ArgParser.parse(args)
     val config: BaseConfig = new BaseConfig(1)
 
+    val p = config.alterPartial({case XSCoreParamsKey => XSCoreParameters})
     val iq: IssueQueue = LazyModule(new IssueQueue()(config.alterPartial({
       case XSCoreParamsKey => XSCoreParameters()
     })))