rob: optimize timing for commit and walk (#1644)

* rob: separate walk and commit valid bits

* rob: optimize instrCnt timing

* rob: fix blockCommit condition when flushPipe

When flushPipe is enabled, it will block commits in ROB. However,
in the deqPtrModule, the commit is not blocked. This commit fixes
the issue.

src/main/scala/xiangshan/Bundle.scala

@@ -371,15 +371,17 @@ class RobCommitInfo(implicit p: Parameters) extends XSBundle {
 }
 
 class RobCommitIO(implicit p: Parameters) extends XSBundle {
+  val isCommit = Output(Bool())
+  val commitValid = Vec(CommitWidth, Output(Bool()))
+
   val isWalk = Output(Bool())
-  val valid = Vec(CommitWidth, Output(Bool()))
   // valid bits optimized for walk
   val walkValid = Vec(CommitWidth, Output(Bool()))
-  val info = Vec(CommitWidth, Output(new RobCommitInfo))
 
-  def hasWalkInstr = isWalk && valid.asUInt.orR
+  val info = Vec(CommitWidth, Output(new RobCommitInfo))
 
-  def hasCommitInstr = !isWalk && valid.asUInt.orR
+  def hasWalkInstr: Bool = isWalk && walkValid.asUInt.orR
+  def hasCommitInstr: Bool = isCommit && commitValid.asUInt.orR
 }
 
 class RSFeedback(implicit p: Parameters) extends XSBundle {

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -342,7 +342,9 @@ class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleI
   // Flushes to frontend may be delayed by some cycles and commit before flush causes errors.
   // Thus, we make all flush reasons to behave the same as exceptions for frontend.
   for (i <- 0 until CommitWidth) {
-    val is_commit = rob.io.commits.valid(i) && !rob.io.commits.isWalk && !rob.io.flushOut.valid
+    // why flushOut: instructions with flushPipe are not commited to frontend
+    // If we commit them to frontend, it will cause flush after commit, which is not acceptable by frontend.
+    val is_commit = rob.io.commits.commitValid(i) && rob.io.commits.isCommit && !rob.io.flushOut.valid
     io.frontend.toFtq.rob_commits(i).valid := RegNext(is_commit)
     io.frontend.toFtq.rob_commits(i).bits := RegEnable(rob.io.commits.info(i), is_commit)
   }
@@ -375,7 +377,7 @@ class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleI
   io.frontend.toFtq.for_redirect_gen.flushRedirect.bits := frontendFlushBits
 
   io.frontend.toFtq.for_redirect_gen.frontendFlushTarget := RegNext(flushTarget)
-  
+
 
   val pendingRedirect = RegInit(false.B)
   when (stage2Redirect.valid) {

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -253,12 +253,10 @@ class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents {
     * Instructions commit: update freelist and rename table
     */
   for (i <- 0 until CommitWidth) {
+    val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i)
+    val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i)
 
     Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) =>
-      // is valid commit req and given instruction has destination register
-      val commitDestValid = io.robCommits.valid(i) && needDestRegCommit(fp, io.robCommits.info(i))
-      XSDebug(p"isFp[${fp}]index[$i]-commitDestValid:$commitDestValid,isWalk:${io.robCommits.isWalk}\n")
-
       /*
       I. RAT Update
        */
@@ -279,14 +277,15 @@ class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents {
       II. Free List Update
        */
       if (fp) { // Float Point free list
-        fpFreeList.io.freeReq(i)  := commitDestValid && !io.robCommits.isWalk
+        fpFreeList.io.freeReq(i)  := commitValid && needDestRegCommit(fp, io.robCommits.info(i))
         fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest
       } else { // Integer free list
         intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid
         intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits
       }
     }
-    intRefCounter.io.deallocate(i).valid := io.robCommits.valid(i) && needDestRegCommit(false, io.robCommits.info(i))
+
+    intRefCounter.io.deallocate(i).valid := (commitValid || walkValid) && needDestRegCommit(false, io.robCommits.info(i))
     intRefCounter.io.deallocate(i).bits := Mux(io.robCommits.isWalk, io.robCommits.info(i).pdest, io.robCommits.info(i).old_pdest)
   }
 
@@ -308,10 +307,10 @@ class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents {
   }
 
   XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n")
-  XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.valid.asUInt)}\n")
+  XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n")
   for (i <- 0 until CommitWidth) {
     val info = io.robCommits.info(i)
-    XSDebug(io.robCommits.isWalk && io.robCommits.valid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " +
+    XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " +
       p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " +
       p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n")
   }

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -105,13 +105,13 @@ class RenameTableWrapper(implicit p: Parameters) extends XSModule {
   intRat.io.readPorts <> io.intReadPorts.flatten
   val intDestValid = io.robCommits.info.map(_.rfWen)
   for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) {
-    arch.wen  := !io.robCommits.isWalk && io.robCommits.valid(i) && intDestValid(i)
+    arch.wen  := io.robCommits.isCommit && io.robCommits.commitValid(i) && intDestValid(i)
     arch.addr := io.robCommits.info(i).ldest
     arch.data := io.robCommits.info(i).pdest
     XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n")
   }
   for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) {
-    spec.wen  := io.robCommits.isWalk && io.robCommits.valid(i) && intDestValid(i)
+    spec.wen  := io.robCommits.isWalk && io.robCommits.walkValid(i) && intDestValid(i)
     spec.addr := io.robCommits.info(i).ldest
     spec.data := io.robCommits.info(i).old_pdest
     XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n")
@@ -128,12 +128,12 @@ class RenameTableWrapper(implicit p: Parameters) extends XSModule {
   fpRat.io.debug_rdata <> io.debug_fp_rat
   fpRat.io.readPorts <> io.fpReadPorts.flatten
   for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) {
-    arch.wen  := !io.robCommits.isWalk && io.robCommits.valid(i) && io.robCommits.info(i).fpWen
+    arch.wen  := io.robCommits.isCommit && io.robCommits.commitValid(i) && io.robCommits.info(i).fpWen
     arch.addr := io.robCommits.info(i).ldest
     arch.data := io.robCommits.info(i).pdest
   }
   for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) {
-    spec.wen  := io.robCommits.isWalk && io.robCommits.valid(i) && io.robCommits.info(i).fpWen
+    spec.wen  := io.robCommits.isWalk && io.robCommits.walkValid(i) && io.robCommits.info(i).fpWen
     spec.addr := io.robCommits.info(i).ldest
     spec.data := io.robCommits.info(i).old_pdest
   }