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体验新版 GitCode,发现更多精彩内容 >>
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63ddece4
编写于
6月 28, 2020
作者:
J
jinyue
浏览文件
操作
浏览文件
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差异文件
Merge branch 'master' into issuequeue
上级
01034290
3434ab78
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
31 addition
and
43 deletion
+31
-43
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+2
-2
src/main/scala/xiangshan/frontend/Ibuffer.scala
src/main/scala/xiangshan/frontend/Ibuffer.scala
+29
-41
未找到文件。
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
63ddece4
...
...
@@ -8,7 +8,7 @@ import xiangshan.backend.rename.FreeListPtr
// Fetch FetchWidth x 32-bit insts from Icache
class
FetchPacket
extends
XSBundle
{
val
instrs
=
Vec
(
FetchWidth
,
UInt
(
32.
W
))
val
mask
=
UInt
(
FetchWidth
.
W
)
val
mask
=
UInt
(
(
FetchWidth
*
2
)
.
W
)
val
pc
=
UInt
(
VAddrBits
.
W
)
// the pc of first inst in the fetch group
}
...
...
@@ -104,4 +104,4 @@ class FrontendToBackendIO extends XSBundle {
// from backend
val
redirect
=
Flipped
(
ValidIO
(
new
Redirect
))
val
commits
=
Vec
(
CommitWidth
,
Flipped
(
ValidIO
(
new
RoqCommit
)))
// update branch pred
}
\ No newline at end of file
}
src/main/scala/xiangshan/frontend/Ibuffer.scala
浏览文件 @
63ddece4
...
...
@@ -13,13 +13,6 @@ class Ibuffer extends XSModule {
val
out
=
Vec
(
DecodeWidth
,
DecoupledIO
(
new
CtrlFlow
))
})
when
(
io
.
in
.
valid
)
{
XSDebug
(
"cache data\n"
)
for
(
i
<-
0
until
FetchWidth
)
{
XSDebug
(
"%b\n"
,
io
.
in
.
bits
.
instrs
(
i
))
}
}
// ignore
for
(
i
<-
0
until
DecodeWidth
)
{
io
.
out
(
i
).
bits
.
exceptionVec
:=
DontCare
...
...
@@ -27,9 +20,13 @@ class Ibuffer extends XSModule {
io
.
out
(
i
).
bits
.
isBr
:=
DontCare
}
//mask initial
// val mask = Wire(Vec(FetchWidth*2, false.B))
// (0 until 16).map(i => mask(i.U) := (io.in.bits.pc(4,1) <= i.U))
// ibuf define
val
ibuf
=
Reg
Init
(
VecInit
(
Seq
.
fill
(
IBufSize
*
2
)(
0.
U
(
16.
W
)
)))
val
ibuf_pc
=
Reg
Init
(
VecInit
(
Seq
.
fill
(
IBufSize
*
2
)(
0.
U
(
VAddrBits
.
W
)
)))
val
ibuf
=
Reg
(
Vec
(
IBufSize
*
2
,
UInt
(
16.
W
)))
val
ibuf_pc
=
Reg
(
Vec
(
IBufSize
*
2
,
UInt
(
VAddrBits
.
W
)))
val
ibuf_valid
=
RegInit
(
VecInit
(
Seq
.
fill
(
IBufSize
*
2
)(
false
.
B
)))
val
head_ptr
=
RegInit
(
0.
U
(
log2Up
(
IBufSize
*
2
).
W
))
val
tail_ptr
=
RegInit
(
0.
U
(
log2Up
(
IBufSize
*
2
).
W
))
...
...
@@ -46,35 +43,22 @@ class Ibuffer extends XSModule {
// enque
when
(
enqValid
)
{
XSInfo
(
"Enque start\n"
)
var
enq_idx
=
0.
U
(
log2Up
(
FetchWidth
*
2
+
1
).
W
)
for
(
i
<-
0
until
FetchWidth
)
{
for
(
i
<-
0
until
FetchWidth
*
2
)
{
when
(
io
.
in
.
bits
.
mask
(
i
))
{
ibuf
(
tail_ptr
+
enq_idx
)
:=
io
.
in
.
bits
.
instrs
(
i
)(
15
,
0
)
ibuf_pc
(
tail_ptr
+
enq_idx
)
:=
io
.
in
.
bits
.
pc
+
enq_idx
+
enq_idx
ibuf
(
tail_ptr
+
enq_idx
)
:=
Mux
(
i
.
U
(
0
),
io
.
in
.
bits
.
instrs
(
i
>>
1
)(
31
,
16
),
io
.
in
.
bits
.
instrs
(
i
>>
1
)(
15
,
0
)
)
ibuf_pc
(
tail_ptr
+
enq_idx
)
:=
io
.
in
.
bits
.
pc
+
(
enq_idx
<<
1
).
asUInt
ibuf_valid
(
tail_ptr
+
enq_idx
)
:=
true
.
B
ibuf
(
tail_ptr
+
enq_idx
+
1.
U
)
:=
io
.
in
.
bits
.
instrs
(
i
)(
31
,
16
)
ibuf_pc
(
tail_ptr
+
enq_idx
+
1.
U
)
:=
io
.
in
.
bits
.
pc
+
enq_idx
+
enq_idx
+
2.
U
ibuf_valid
(
tail_ptr
+
enq_idx
+
1.
U
)
:=
true
.
B
XSDebug
(
"Enque: %b\n"
,
io
.
in
.
bits
.
instrs
(
i
)(
15
,
0
))
XSDebug
(
"Enque: %b\n"
,
io
.
in
.
bits
.
instrs
(
i
)(
31
,
16
))
}
enq_idx
=
enq_idx
+
io
.
in
.
bits
.
mask
(
i
)
+
io
.
in
.
bits
.
mask
(
i
)
enq_idx
=
enq_idx
+
io
.
in
.
bits
.
mask
(
i
)
}
tail_ptr
:=
tail_ptr
+
enq_idx
last_enq
:=
true
.
B
XSInfo
(
"Enque finished, tail_ptr=%d\n"
,
tail_ptr
+
enq_idx
)
}
// deque
when
(
deqValid
)
{
XSInfo
(
"Deque start\n"
)
var
deq_idx
=
0.
U
(
log2Up
(
DecodeWidth
*
2
+
1
).
W
)
for
(
i
<-
0
until
DecodeWidth
)
{
when
(
io
.
out
(
i
).
ready
&&
ibuf_valid
(
head_ptr
+
deq_idx
))
{
...
...
@@ -82,8 +66,6 @@ class Ibuffer extends XSModule {
// is RVC
io
.
out
(
i
).
bits
.
instr
:=
Cat
(
0.
U
(
16.
W
),
ibuf
(
head_ptr
+
deq_idx
))
io
.
out
(
i
).
bits
.
pc
:=
ibuf_pc
(
head_ptr
+
deq_idx
)
XSDebug
(
"%b[RVC] PC=%d\n"
,
Cat
(
0.
U
(
16.
W
),
ibuf
(
head_ptr
+
deq_idx
)),
ibuf_pc
(
head_ptr
+
deq_idx
))
io
.
out
(
i
).
bits
.
isRVC
:=
true
.
B
io
.
out
(
i
).
valid
:=
true
.
B
ibuf_valid
(
head_ptr
+
deq_idx
)
:=
false
.
B
...
...
@@ -91,8 +73,6 @@ class Ibuffer extends XSModule {
// isn't RVC
io
.
out
(
i
).
bits
.
instr
:=
Cat
(
ibuf
(
head_ptr
+
deq_idx
+
1.
U
),
ibuf
(
head_ptr
+
deq_idx
))
io
.
out
(
i
).
bits
.
pc
:=
ibuf_pc
(
head_ptr
+
deq_idx
)
XSDebug
(
"%b[NORVC] PC=%d\n"
,
Cat
(
ibuf
(
head_ptr
+
deq_idx
+
1.
U
),
ibuf
(
head_ptr
+
deq_idx
)),
ibuf_pc
(
head_ptr
+
deq_idx
))
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
io
.
out
(
i
).
valid
:=
true
.
B
ibuf_valid
(
head_ptr
+
deq_idx
)
:=
false
.
B
...
...
@@ -100,15 +80,11 @@ class Ibuffer extends XSModule {
}.
otherwise
{
// half inst keep in buffer
io
.
out
(
i
).
bits
.
instr
:=
0.
U
(
32.
W
)
XSWarn
(
"This is half inst\n"
)
io
.
out
(
i
).
bits
.
pc
:=
0.
U
(
VAddrBits
.
W
)
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
io
.
out
(
i
).
valid
:=
false
.
B
}
}.
otherwise
{
XSWarn
(
"This output is not ready, or buffer is empty\n"
)
io
.
out
(
i
).
bits
.
instr
:=
0.
U
io
.
out
(
i
).
bits
.
pc
:=
0.
U
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
...
...
@@ -119,15 +95,14 @@ class Ibuffer extends XSModule {
// when RVC deque, deq_idx+1
// when not RVC deque, deq_idx+2
// when only have half inst, keep it in buffer
deq_idx
=
deq_idx
+
(
io
.
out
(
i
).
ready
&&
ibuf_valid
(
head_ptr
+
deq_idx
)
&&
ibuf
(
head_ptr
+
deq_idx
)(
1
,
0
)
=/=
"b11"
.
U
)
+
(
io
.
out
(
i
).
ready
&&
ibuf_valid
(
head_ptr
+
deq_idx
)
&&
!(
ibuf
(
head_ptr
+
deq_idx
)(
1
,
0
)
=/=
"b11"
.
U
)
&&
ibuf_valid
(
head_ptr
+
deq_idx
+
1.
U
))
+
(
io
.
out
(
i
).
ready
&&
ibuf_valid
(
head_ptr
+
deq_idx
)
&&
!(
ibuf
(
head_ptr
+
deq_idx
)(
1
,
0
)
=/=
"b11"
.
U
)
&&
ibuf_valid
(
head_ptr
+
deq_idx
+
1.
U
))
deq_idx
=
deq_idx
+
PriorityMux
(
Seq
(
!(
io
.
out
(
i
).
ready
&&
ibuf_valid
(
head_ptr
+
deq_idx
))
->
0.
U
,
(
ibuf
(
head_ptr
+
deq_idx
)(
1
,
0
)
=/=
"b11"
.
U
)
->
1.
U
,
ibuf_valid
(
head_ptr
+
deq_idx
+
1.
U
)
->
2.
U
))
}
head_ptr
:=
head_ptr
+
deq_idx
XSInfo
(
"Deque finished\n"
)
XSInfo
(
"head_prt=%d, tail_ptr=%d\n"
,
head_ptr
+
deq_idx
,
tail_ptr
)
last_enq
:=
false
.
B
}.
otherwise
{
for
(
i
<-
0
until
DecodeWidth
)
{
...
...
@@ -140,7 +115,6 @@ class Ibuffer extends XSModule {
// flush
when
(
io
.
flush
)
{
XSInfo
(
"Flush signal received, clear buffer\n"
)
for
(
i
<-
0
until
IBufSize
)
{
ibuf_valid
(
i
)
:=
false
.
B
head_ptr
:=
0.
U
...
...
@@ -151,4 +125,18 @@ class Ibuffer extends XSModule {
io
.
out
(
i
).
valid
:=
false
.
B
}
}
//Debug Info
// XSDebug(enqValid, "Enque:\n")
// for(i <- 0 until FetchWidth) {
// XSDebug(enqValid, p"${Binary(io.in.bits.instrs(i))}\n")
// }
XSInfo
(
io
.
flush
,
"Flush signal received, clear buffer\n"
)
XSDebug
(
deqValid
,
"Deque:\n"
)
for
(
i
<-
0
until
DecodeWidth
)
{
XSDebug
(
deqValid
,
p
"${Binary(io.out(i).bits.instr)} PC=${Hexadecimal(io.out(i).bits.pc)}\n"
)
}
// XSDebug(enqValid, p"last_head_ptr=$head_ptr last_tail_ptr=$tail_ptr\n")
// XSInfo(full, "Queue is full\n")
}
\ No newline at end of file
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