Rewrite AXI4Timer, Add AXI4Timer Test

src/main/scala/device/AXI4SlaveModule.scala

@@ -36,7 +36,7 @@ class AXI4SlaveModuleImp[T<:Data](outer: AXI4SlaveModule[T])
   extends LazyModuleImp(outer)
 {
   val io = IO(new Bundle {
-    val extra = Option(outer._extra)
+    val extra = Option(outer._extra.cloneType)
   })
 
   val (in, edge) = outer.node.in.head

src/main/scala/device/AXI4Timer.scala

 package device
 
 import chisel3._
-import chisel3.util._
 import chisel3.util.experimental.BoringUtils
-import bus.axi4._
+import chipsalliance.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.AddressSet
 import utils._
 
 class TimerIO extends Bundle {
   val mtip = Output(Bool())
 }
 
-class AXI4Timer(sim: Boolean = false) extends AXI4SlaveModule(new AXI4Lite, new TimerIO) {
-  val mtime = RegInit(0.U(64.W))  // unit: us
-  val mtimecmp = RegInit(0.U(64.W))
-
-  val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 10000)
-  val freq = RegInit(clk.U(16.W))
-  val inc = RegInit(1000.U(16.W))
-
-  val cnt = RegInit(0.U(16.W))
-  val nextCnt = cnt + 1.U
-  cnt := Mux(nextCnt < freq, nextCnt, 0.U)
-  val tick = (nextCnt === freq)
-  when (tick) { mtime := mtime + inc }
-
-  if (sim) {
-    val isWFI = WireInit(false.B)
-    BoringUtils.addSink(isWFI, "isWFI")
-    when (isWFI) { mtime := mtime + 100000.U }
+class AXI4Timer
+(
+  sim: Boolean = false,
+  address: AddressSet
+)(implicit p: Parameters)
+  extends AXI4SlaveModule(address, executable = false, _extra = new TimerIO)
+{
+  override lazy val module = new AXI4SlaveModuleImp[TimerIO](this){
+    val mtime = RegInit(0.U(64.W))  // unit: us
+    val mtimecmp = RegInit(0.U(64.W))
+
+    val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 10000)
+    val freq = RegInit(clk.U(16.W))
+    val inc = RegInit(1000.U(16.W))
+
+    val cnt = RegInit(0.U(16.W))
+    val nextCnt = cnt + 1.U
+    cnt := Mux(nextCnt < freq, nextCnt, 0.U)
+    val tick = (nextCnt === freq)
+    when (tick) { mtime := mtime + inc }
+
+    if (sim) {
+      val isWFI = WireInit(false.B)
+      BoringUtils.addSink(isWFI, "isWFI")
+      when (isWFI) { mtime := mtime + 100000.U }
+    }
+
+    val mapping = Map(
+      RegMap(0x4000, mtimecmp),
+      RegMap(0x8000, freq),
+      RegMap(0x8008, inc),
+      RegMap(0xbff8, mtime)
+    )
+    def getOffset(addr: UInt) = addr(15,0)
+
+    RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
+      getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
+
+    io.extra.get.mtip := RegNext(mtime >= mtimecmp)
   }
-
-  val mapping = Map(
-    RegMap(0x4000, mtimecmp),
-    RegMap(0x8000, freq),
-    RegMap(0x8008, inc),
-    RegMap(0xbff8, mtime)
-  )
-  def getOffset(addr: UInt) = addr(15,0)
-
-  RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
-    getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
-
-  io.extra.get.mtip := RegNext(mtime >= mtimecmp)
 }

src/test/scala/device/AXI4TimerTest.scala

+package device
+
+import chipsalliance.rocketchip.config._
+import chisel3._
+import chiseltest._
+import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4UserYanker}
+import org.scalatest.{FlatSpec, Matchers}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.diplomacy._
+import utils.DebugIdentityNode
+
+
+class AXI4TimerTestTop(implicit p: Parameters) extends LazyModule {
+
+  val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
+  val fuzz = LazyModule(new TLFuzzer(nOperations = 10, overrideAddress = Some(addressSet), inFlight = 1))
+  val ident = LazyModule(new DebugIdentityNode())
+  val axiTimer = LazyModule(new AXI4Timer(sim = true, addressSet))
+
+  axiTimer.node :=
+    AXI4UserYanker() :=
+    TLToAXI4() :=
+    ident.node :=
+    fuzz.node
+
+  lazy val module = new LazyModuleImp(this){
+    val finished = IO(Output(Bool()))
+    finished := fuzz.module.io.finished
+  }
+
+}
+
+class AXI4TimerTest extends FlatSpec with Matchers with ChiselScalatestTester {
+  it should "run" in {
+    implicit val p = Parameters.empty
+    test(LazyModule(new AXI4TimerTestTop()).module){ c =>
+      while (!c.finished.peek().litToBoolean){
+        c.clock.step(1)
+      }
+    }
+  }
+}
+