Impl TLTimer

src/main/scala/device/TLTimer.scala

+package device
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.tilelink._
+import chipsalliance.rocketchip.config
+import chipsalliance.rocketchip.config._
+import chisel3.util.experimental.BoringUtils
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper.{RegField, RegWriteFn}
+import utils.{HoldUnless, MaskExpand, RegMap}
+
+class TLTimer(address: Seq[AddressSet], sim: Boolean)(implicit p: Parameters) extends LazyModule {
+
+  val device = new SimpleDevice("clint", Seq("XiangShan", "clint"))
+  val node = TLRegisterNode(address, device, beatBytes = 8)
+
+  lazy val module = new LazyModuleImp(this){
+    val mtip = IO(Output(Bool()))
+
+    val mtime = RegInit(0.U(64.W))  // unit: us
+    val mtimecmp = RegInit(0.U(64.W))
+
+    val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 100)
+    val freq = RegInit(clk.U(16.W))
+    val inc = RegInit(1000.U(16.W))
+
+    val cnt = RegInit(0.U(16.W))
+    val nextCnt = cnt + 1.U
+    cnt := Mux(nextCnt < freq, nextCnt, 0.U)
+    val tick = (nextCnt === freq)
+    when (tick) { mtime := mtime + inc }
+
+    if (sim) {
+      val isWFI = WireInit(false.B)
+      BoringUtils.addSink(isWFI, "isWFI")
+      when (isWFI) { mtime := mtime + 100000.U }
+    }
+
+    node.regmap( mapping =
+      0x4000 -> RegField.bytes(mtimecmp),
+      0x8000 -> RegField.bytes(freq),
+      0x8008 -> RegField.bytes(inc),
+      0xbff8 -> RegField.bytes(mtime)
+    )
+
+    printf(p"[Timer] mtime=$mtime cnt=$cnt freq=$freq\n")
+
+    mtip := RegNext(mtime >= mtimecmp)
+  }
+}

src/main/scala/utils/DebugIdentityNode.scala

+package utils
+
+import chisel3._
+import chipsalliance.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.tilelink.{TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters}
+
+class DebugIdentityNode()(implicit p: Parameters) extends LazyModule {
+
+  val node = TLIdentityNode()
+
+  val n = TLClientNode(Seq(TLMasterPortParameters.v1(
+    Seq(
+      TLMasterParameters.v1("debug node")
+    )
+  )))
+
+  lazy val module = new LazyModuleImp(this){
+    val (out, _) = node.out(0)
+    val (in, _) = node.in(0)
+    when(in.a.fire()){
+      printf(p"[A] addr: ${Hexadecimal(in.a.bits.address)} " +
+        p"opcode: ${in.a.bits.opcode} data: ${Hexadecimal(in.a.bits.data)}\n"
+      )
+    }
+    when(in.d.fire()){
+      printf(p"[D] opcode: ${in.d.bits.opcode} data: ${Hexadecimal(in.d.bits.data)}\n")
+    }
+  }
+}

src/test/scala/device/TLTimerTest.scala

+package device
+
+import chipsalliance.rocketchip.config._
+import chisel3._
+import chiseltest._
+import org.scalatest.{FlatSpec, Matchers}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.diplomacy._
+import utils.DebugIdentityNode
+
+class TLTimerTestTop()(implicit p: Parameters) extends LazyModule {
+
+
+  val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
+
+  val timer = LazyModule(new TLTimer(Seq(addressSet), sim = true))
+  val ident = LazyModule(new DebugIdentityNode)
+  val fuzz = LazyModule(new TLFuzzer(
+    nOperations = 10,
+    overrideAddress = Some(addressSet)
+  ))
+
+  timer.node := ident.node := TLDelayer(0.1) := fuzz.node
+
+  lazy val module = new LazyModuleImp(this){
+    val io = IO(new Bundle() {
+      val finished = Output(Bool())
+    })
+    io.finished := fuzz.module.io.finished
+  }
+}
+
+class TLTimerTest extends FlatSpec with ChiselScalatestTester with Matchers {
+
+  it should "run" in {
+    implicit val p = Parameters.empty
+    test(LazyModule(new TLTimerTestTop()).module){ c =>
+      while (!c.io.finished.peek().litToBoolean){
+        c.clock.step(1)
+      }
+    }
+  }
+
+}