io.out.valid:=io.in.valid&&io.metaReadBus.req.ready&&io.dataReadBus.req.ready&&io.s2s3Empty// FIXME: remove me when do not use nut's cache
io.in.ready:=(!io.in.valid||io.out.fire())&&io.metaReadBus.req.ready&&io.dataReadBus.req.ready&&io.s2s3Empty// FIXME: remove me when do not use nut's cache
Debug(){
if(debug){
...
...
@@ -181,7 +183,7 @@ sealed class CacheStage2(implicit val cacheConfig: CacheConfig) extends CacheMod
// io.out.cf.exceptionVec(instrAccessFault) := io.in.pc(VAddrBits - 1, PAddrBits).orR && !vmEnable // NOTE: PAddrBits is larger than VAddrBits, so comment it
io.out.ctrl.noSpecExec:=io.out.ctrl.isXSTrap||io.out.ctrl.fuType===FuType.csr||io.out.ctrl.fuType===FuType.mou||(io.out.ctrl.fuType===FuType.alu&&io.out.ctrl.fuOpType===ALUOpType.sfence/*noSpecExec make it sent to alu0,for roq is empty*/)
//io.out.ctrl.isBlocked := (io.out.ctrl.fuType===FuType.alu && io.out.ctrl.fuOpType===ALUOpType.sfence) // TOOD: check it
csrExceptionVec(illegalInstr):=isIllegalAddr&&wen// Trigger an illegal instr exception when unimplemented csr is being read/written
csrExceptionVec(illegalInstr):=isIllegalAddr&&wen// Trigger an illegal instr exception when unimplemented csr is being read/written // TODO: if csrrw under wrong priv mode will cause illegal instr now ?
@@ -681,7 +615,13 @@ class Lsroq extends XSModule {
}
when(io.uncache.req.fire()){
XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n",uop(missRefillSel).cf.pc,io.dcache.req.bits.addr,io.uncache.req.bits.data,io.uncache.req.bits.cmd,io.uncache.req.bits.mask)
XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n",