[WIP] loadPipeline: fix wiring for loadPipeline

src/main/scala/xiangshan/backend/Backend.scala

@@ -58,6 +58,15 @@ class Backend extends XSModule
     hasZero = false
   ))
 
+  // decode.io := DontCare
+  // brq.io := DontCare
+  // decBuf.io := DontCare
+  // rename.io := DontCare
+  // dispatch.io := DontCare
+  // roq.io := DontCare
+  // intRf.io := DontCare
+  // fpRf.io := DontCare
+
   // backend redirect, flush pipeline
   val redirect = Mux(
     roq.io.redirect.valid,
@@ -108,7 +117,6 @@ class Backend extends XSModule
       wakeUpPort.valid := exuOut.valid
     }
 
-
     cfg match {
       case Exu.ldExeUnitCfg =>
       case Exu.stExeUnitCfg =>
@@ -120,7 +128,7 @@ class Backend extends XSModule
     rs
   })
 
-  for( rs <- reservedStations){
+  for(rs <- reservedStations){
     rs.io.bypassUops <> reservedStations.
       filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)).
       map(_.io.selectedUop)

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -37,10 +37,10 @@ class Dispatch extends XSModule {
     val lsIdxs = Input(Vec(RenameWidth, new LSIdx))
     val commits = Input(Vec(CommitWidth, Valid(new RoqCommit)))
     // read regfile
-    val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
+    val readIntRf = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort))
     val readFpRf = Vec(NRFpReadPorts, Flipped(new RfReadPort))
     // read reg status (busy/ready)
-    val intPregRdy = Vec(NRIntReadPorts, Input(Bool()))
+    val intPregRdy = Vec(NRIntReadPorts - NRMemReadPorts, Input(Bool()))
     val fpPregRdy = Vec(NRFpReadPorts, Input(Bool()))
     // load + store reg status (busy/ready)
     val memIntRf = Vec(NRMemReadPorts, Flipped(new RfReadPort))
@@ -136,7 +136,7 @@ class Dispatch extends XSModule {
     fpDq.io.deq <> DontCare
     io.readFpRf <> DontCare
   }
-
+  
   // Load/store dispatch queue to load/store issue queues
   val lsDispatch = Module(new Dispatch2Ls)
   lsDispatch.io.fromDq <> lsDq.io.deq
@@ -146,4 +146,5 @@ class Dispatch extends XSModule {
   lsDispatch.io.fpRegRdy <> io.fpMemRegRdy
   lsDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
   lsDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
+  lsDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -10,8 +10,8 @@ import xiangshan.backend.exu._
 class Dispatch2Int extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp)))
-    val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
-    val regRdy = Vec(NRIntReadPorts, Input(Bool()))
+    val readRf = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort))
+    val regRdy = Vec(NRIntReadPorts - NRMemReadPorts, Input(Bool()))
     val numExist = Input(Vec(exuParameters.IntExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp))
     val enqIQData = Vec(exuParameters.IntExuCnt, Output(new ExuInput))

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -11,9 +11,9 @@ class Rename extends XSModule {
     val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
     val wbIntResults = Vec(NRIntWritePorts, Flipped(ValidIO(new ExuOutput)))
     val wbFpResults = Vec(NRFpWritePorts, Flipped(ValidIO(new ExuOutput)))
-    val intRfReadAddr = Vec(NRIntReadPorts + NRMemReadPorts, Input(UInt(PhyRegIdxWidth.W)))
+    val intRfReadAddr = Vec(NRIntReadPorts, Input(UInt(PhyRegIdxWidth.W)))
     val fpRfReadAddr = Vec(NRFpReadPorts, Input(UInt(PhyRegIdxWidth.W)))
-    val intPregRdy = Vec(NRIntReadPorts + NRMemReadPorts, Output(Bool()))
+    val intPregRdy = Vec(NRIntReadPorts, Output(Bool()))
     val fpPregRdy = Vec(NRFpReadPorts, Output(Bool()))
     // set preg to busy when replay
     val replayPregReq = Vec(ReplayWidth, Input(new ReplayPregReq))

src/main/scala/xiangshan/cache/dcacheWrapper.scala

@@ -258,6 +258,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   for (w <- 0 until LoadPipelineWidth) {
     val load_w_nack = nack_load(io.lsu.load(w).req.bits.addr)
     ldu(w).io.lsu.req <> io.lsu.load(w).req
+    ldu(w).io.lsu.s1_paddr <> io.lsu.load(w).s1_paddr
     ldu(w).io.nack := load_w_nack
     XSDebug(load_w_nack, s"LoadUnit $w nacked\n")
 

src/main/scala/xiangshan/mem/Memend.scala

@@ -35,12 +35,13 @@ object genWdata {
 class LsPipelineBundle extends XSBundle {
   val vaddr = UInt(VAddrBits.W)
   val paddr = UInt(PAddrBits.W)
-  val func = UInt(6.W)
+  val func = UInt(6.W) //fixme???
   val mask = UInt(8.W)
   val data = UInt(XLEN.W)
   val uop = new MicroOp
 
   val miss = Bool()
+  val tlbMiss = Bool()
   val mmio = Bool()
   val rollback = Bool()
 

src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala

@@ -160,12 +160,6 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
   io.dcache.req.bits.mask := DontCare
 
   io.dcache.req.bits.meta.id       := DontCare // TODO: // FIXME
-  io.dcache.req.bits.meta.vaddr    := DontCare // data(missRefillSel).vaddr
-  io.dcache.req.bits.meta.paddr    := missRefillBlockAddr
-  io.dcache.req.bits.meta.uop      := uop(missRefillSel)
-  io.dcache.req.bits.meta.mmio     := false.B // data(missRefillSel).mmio
-  io.dcache.req.bits.meta.tlb_miss := false.B
-  io.dcache.req.bits.meta.mask     := DontCare
   io.dcache.req.bits.meta.replay   := false.B
 
   io.dcache.resp.ready := true.B

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -42,6 +42,17 @@ class LoadUnit_S0 extends XSModule {
   io.dcacheReq.bits.cmd  := MemoryOpConstants.M_XRD
   io.dcacheReq.bits.addr := s0_vaddr
   io.dcacheReq.bits.mask := s0_mask
+  io.dcacheReq.bits.data := DontCare
+
+  // TODO: update cache meta
+  io.dcacheReq.bits.meta.id       := DontCare
+  io.dcacheReq.bits.meta.vaddr    := s0_vaddr
+  io.dcacheReq.bits.meta.paddr    := DontCare
+  io.dcacheReq.bits.meta.uop      := s0_uop
+  io.dcacheReq.bits.meta.mmio     := false.B
+  io.dcacheReq.bits.meta.tlb_miss := false.B
+  io.dcacheReq.bits.meta.mask     := s0_mask
+  io.dcacheReq.bits.meta.replay   := false.B
 
   val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List(
     "b00".U   -> true.B,                   //b
@@ -103,6 +114,7 @@ class LoadUnit_S1 extends XSModule {
   io.out.bits := io.in.bits
   io.out.bits.paddr := s1_paddr
   io.out.bits.mmio := s1_mmio
+  io.out.bits.tlbMiss := s1_tlb_miss
   io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld
 
   io.in.ready := io.out.ready || !io.in.valid
@@ -127,6 +139,23 @@ class LoadUnit_S2 extends XSModule {
   val s2_paddr = io.in.bits.paddr
   val s2_cache_miss = io.dcacheResp.bits.miss
 
+  // load forward query datapath
+  io.sbuffer.valid := io.in.valid
+  io.sbuffer.paddr := s2_paddr
+  io.sbuffer.uop := s2_uop
+  io.sbuffer.sqIdx := s2_uop.sqIdx
+  io.sbuffer.lsroqIdx := s2_uop.lsroqIdx
+  io.sbuffer.mask := s2_mask
+  io.sbuffer.pc := s2_uop.cf.pc // FIXME: remove it
+  
+  io.lsroq.valid := io.in.valid
+  io.lsroq.paddr := s2_paddr
+  io.lsroq.uop := s2_uop
+  io.lsroq.sqIdx := s2_uop.sqIdx
+  io.lsroq.lsroqIdx := s2_uop.lsroqIdx
+  io.lsroq.mask := s2_mask
+  io.lsroq.pc := s2_uop.cf.pc // FIXME: remove it
+
   io.dcacheResp.ready := true.B
   assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost")
 
@@ -203,6 +232,7 @@ class LoadUnit extends XSModule {
   load_s1.io.redirect <> io.redirect
   load_s1.io.tlbFeedback <> io.tlbFeedback
   load_s1.io.dtlbResp <> io.dtlb.resp
+  load_s1.io.s1_kill <> io.dcache.s1_kill
   io.sbuffer <> load_s1.io.forward
   io.lsroq.forward <> load_s1.io.forward
 
@@ -247,6 +277,7 @@ class LoadUnit extends XSModule {
   load_s2.io.out.ready := true.B
   io.lsroq.ldout.ready := !hitLoadOut.valid
   io.ldout.bits := Mux(load_s2.io.out.ready, hitLoadOut.bits, io.lsroq.ldout.bits)
+  io.ldout.valid := hitLoadOut.valid || io.lsroq.ldout.valid
 
   when(io.ldout.fire()){
     XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen)