rename: speculatively assign roqIdx to uop for better timing in dispatch1

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -101,7 +101,8 @@ class Dispatch1 extends XSModule with HasExceptionNO {
     // update commitType
     updatedUop(i).ctrl.commitType := updatedCommitType(i)
     // update roqIdx, lqIdx, sqIdx
-    updatedUop(i).roqIdx := io.enqRoq.resp(i)
+    // updatedUop(i).roqIdx := io.enqRoq.resp(i)
+    XSError(io.fromRename(i).valid && updatedUop(i).roqIdx.asUInt =/= io.enqRoq.resp(i).asUInt, "they should equal")
     updatedUop(i).lqIdx  := io.enqLsq.resp(i).lqIdx
     updatedUop(i).sqIdx  := io.enqLsq.resp(i).sqIdx
   }

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import utils._
+import xiangshan.backend.roq.RoqPtr
 
 class RenameBypassInfo extends XSBundle {
   val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
@@ -12,7 +13,7 @@ class RenameBypassInfo extends XSBundle {
   val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
 }
 
-class Rename extends XSModule {
+class Rename extends XSModule with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
     val roqCommits = Flipped(new RoqCommitIO)
@@ -51,6 +52,7 @@ class Rename extends XSModule {
     freelist.redirect := io.redirect
     freelist.walk.valid := io.roqCommits.isWalk
   }
+  val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk
 
   def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = {
     {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)}
@@ -64,6 +66,16 @@ class Rename extends XSModule {
   fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready
   intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready
 
+  // speculatively assign the instruction with an roqIdx
+  val validCount = PopCount(io.in.map(_.valid))
+  val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr))
+  val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.isUnconditional() && !io.redirect.bits.flushItself())
+  val roqIdxHeadNext = Mux(io.redirect.valid,
+    Mux(io.redirect.bits.isUnconditional(), 0.U.asTypeOf(new RoqPtr), io.redirect.bits.roqIdx),
+    Mux(lastCycleMisprediction, roqIdxHead + 1.U, Mux(canOut, roqIdxHead + validCount, roqIdxHead))
+  )
+  roqIdxHead := roqIdxHeadNext
+
   /**
     * Rename: allocate free physical register and update rename table
     */
@@ -85,7 +97,6 @@ class Rename extends XSModule {
   val needFpDest = Wire(Vec(RenameWidth, Bool()))
   val needIntDest = Wire(Vec(RenameWidth, Bool()))
   val hasValid = Cat(io.in.map(_.valid)).orR
-  val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk
   for (i <- 0 until RenameWidth) {
     uops(i).cf := io.in(i).bits.cf
     uops(i).ctrl := io.in(i).bits.ctrl
@@ -115,6 +126,8 @@ class Rename extends XSModule {
       )
     )
 
+    uops(i).roqIdx := roqIdxHead + i.U
+
     io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk
     io.out(i).bits := uops(i)