lvna: make hasprefetch enable

huancun @ cfb67072

-Subproject commit e85243297b2a27e306a159a639dfc87f3660c46e
+Subproject commit cfb67072aee1a48779ddb7124f08769d0d2d6fba

src/main/scala/top/Configs.scala

@@ -236,7 +236,8 @@ class WithNKBL2
   ways: Int = 8,
   inclusive: Boolean = true,
   banks: Int = 1,
-  alwaysReleaseData: Boolean = false
+  alwaysReleaseData: Boolean = false,
+  hasPrefetch: Boolean = true,
 ) extends Config((site, here, up) => {
   case XSTileKey =>
     val upParams = up(XSTileKey)
@@ -258,7 +259,7 @@ class WithNKBL2
         )),
         reqField = Seq(PreferCacheField()),
         echoField = Seq(DirtyField()),
-        prefetch = Some(huancun.prefetch.PrefetchReceiverParams()),
+        prefetch = if (hasPrefetch) Some(huancun.prefetch.PrefetchReceiverParams()) else None,
         enablePerf = true,
         sramDepthDiv = 2,
         tagECC = None,
@@ -495,6 +496,15 @@ class NohypeSimConfig(n: Int = 1) extends Config(
     ++ new MinimalConfig(n)
 )
 
+class LvNASingleSimConfig(n: Int = 1) extends Config(
+  new WithLvNANKBL3(256, inclusive = false, banks = 1)
+    ++ new WithNohypeOffsetDevices(0x3000000)
+    ++ new WithLvNATile(n)
+    ++ new WithNKBL2(64, inclusive = false, alwaysReleaseData = true, hasPrefetch = false)
+    // ++ new WithNKBL1D(64)
+    ++ new MinimalConfig(n)
+)
+
 class NohypeFPGAConfig(n: Int = 1) extends Config(
   new WithLvNANKBL3(4096, inclusive = false, banks = 4)
     ++ new WithLvNATile(n)

src/main/scala/xiangshan/Parameters.scala

@@ -257,6 +257,8 @@ case class XSCoreParameters
       Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
 
   val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
+
+  val unusedDsid = ((1 << DsidWidth) - 1).U(DsidWidth.W)
 }
 
 case object DebugOptionsKey extends Field[DebugOptions]