lsq: simplify allowEnqueue logic

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -578,13 +578,7 @@ class LoadQueue extends XSModule
   val lastLastCycleRedirect = RegNext(lastCycleRedirect.valid)
   val validCount = distanceBetween(enqPtrExt(0), deqPtrExt)
 
-  allowEnqueue := Mux(io.brqRedirect.valid,
-    false.B,
-    Mux(lastLastCycleRedirect,
-      validCount <= (LoadQueueSize - RenameWidth).U,
-      validCount + enqNumber <= (LoadQueueSize - RenameWidth).U
-    )
-  )
+  allowEnqueue := validCount + enqNumber <= (LoadQueueSize - RenameWidth).U
 
   // debug info
   XSDebug("enqPtrExt %d:%d deqPtrExt %d:%d\n", enqPtrExt(0).flag, enqPtr, deqPtrExt.flag, deqPtr)

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -353,13 +353,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
   val dequeueCount = Mux(io.sbuffer(1).fire(), 2.U, Mux(io.sbuffer(0).fire() || io.mmioStout.fire(), 1.U, 0.U))
   val validCount = distanceBetween(enqPtrExt(0), deqPtrExt(0))
 
-  allowEnqueue := Mux(io.brqRedirect.valid,
-    false.B,
-    Mux(lastLastCycleRedirect,
-      validCount <= (StoreQueueSize - RenameWidth).U,
-      validCount + enqNumber <= (StoreQueueSize - RenameWidth).U
-    )
-  )
+  allowEnqueue := validCount + enqNumber <= (StoreQueueSize - RenameWidth).U
 
   // io.sqempty will be used by sbuffer
   // We delay it for 1 cycle for better timing