noop,CSR: use S-mode CSRs to temporarily match riscv32-nemu

* now we can run hello over Nanos-lite

src/main/scala/noop/CSR.scala

@@ -18,23 +18,26 @@ object CSRInstr extends HasInstrType {
   def CSRRS   = BitPat("b????????????_?????_010_?????_1110011")
   def ECALL   = BitPat("b001100000010_00000_000_00000_1110011")
   def MRET    = BitPat("b000000000000_00000_000_00000_1110011")
+  def SRET    = BitPat("b000100000010_00000_000_00000_1110011")
 
   val table = Array(
     CSRRW          -> List(InstrI, FuType.csr, CSROpType.wrt),
     CSRRS          -> List(InstrI, FuType.csr, CSROpType.set),
     ECALL          -> List(InstrI, FuType.csr, CSROpType.jmp),
-    MRET           -> List(InstrI, FuType.csr, CSROpType.jmp)
+    MRET           -> List(InstrI, FuType.csr, CSROpType.jmp),
+    SRET           -> List(InstrI, FuType.csr, CSROpType.jmp)
   )
 }
 
 trait HasCSRConst {
-  val Mstatus       = 0x300
-  val Mtvec         = 0x305
-  val Mepc          = 0x341
-  val Mcause        = 0x342
+  // these are actually S-mode CSRs to match riscv32-nemu
+  val Mstatus       = 0x100
+  val Mtvec         = 0x105
+  val Mepc          = 0x141
+  val Mcause        = 0x142
 
   def privEcall = 0x000.U
-  def privMret  = 0x302.U
+  def privMret  = 0x102.U
 }
 
 class CSRIO extends FunctionUnitIO {
@@ -58,7 +61,7 @@ class CSR(implicit val p: NOOPConfig) extends Module with HasCSRConst {
 
   val mtvec = Reg(UInt(32.W))
   val mcause = Reg(UInt(32.W))
-  val mstatus = Reg(UInt(32.W))
+  val mstatus = RegInit("h000c0100".U)
   val mepc = Reg(UInt(32.W))
 
   val hasPerfCnt = !p.FPGAPlatform
@@ -100,7 +103,7 @@ class CSR(implicit val p: NOOPConfig) extends Module with HasCSRConst {
   val isEcall = (addr === privEcall) && !isException
   val exceptionNO = Mux1H(List(
     io.isInvOpcode -> 2.U,
-    isEcall -> 11.U
+    isEcall -> 9.U //11.U
   ))
 
   io.redirect.valid := (valid && func === CSROpType.jmp) || isException