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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
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5374af55
编写于
4月 12, 2022
作者:
Y
Yinan Xu
浏览文件
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电子邮件补丁
差异文件
temp
上级
da16375f
变更
10
隐藏空白更改
内联
并排
Showing
10 changed file
with
27 addition
and
27 deletion
+27
-27
src/main/scala/top/Configs.scala
src/main/scala/top/Configs.scala
+1
-1
src/main/scala/utils/Misc.scala
src/main/scala/utils/Misc.scala
+3
-3
src/main/scala/xiangshan/backend/issue/StatusArray.scala
src/main/scala/xiangshan/backend/issue/StatusArray.scala
+4
-3
src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
...main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
+1
-3
src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
...ain/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
+11
-8
src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
+1
-1
src/main/scala/xiangshan/cache/mmu/PTW.scala
src/main/scala/xiangshan/cache/mmu/PTW.scala
+2
-2
src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
+1
-1
src/main/scala/xiangshan/cache/mmu/Repeater.scala
src/main/scala/xiangshan/cache/mmu/Repeater.scala
+2
-2
src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
...main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
+1
-3
未找到文件。
src/main/scala/top/Configs.scala
浏览文件 @
5374af55
...
...
@@ -298,7 +298,7 @@ class MediumConfig(n: Int = 1) extends Config(
)
class
DefaultConfig
(
n
:
Int
=
1
)
extends
Config
(
new
WithNKBL3
(
6
*
1024
,
inclusive
=
false
,
banks
=
4
,
ways
=
6
)
new
WithNKBL3
(
2
*
1024
,
inclusive
=
false
,
banks
=
4
,
ways
=
8
)
++
new
WithNKBL2
(
2
*
512
,
inclusive
=
false
,
banks
=
4
,
alwaysReleaseData
=
true
)
++
new
WithNKBL1D
(
128
)
++
new
BaseConfig
(
n
)
...
...
src/main/scala/utils/Misc.scala
浏览文件 @
5374af55
...
...
@@ -89,13 +89,13 @@ object Transpose
* assert when 'signal' is true for more than 'threshold' cycles
*/
object
TimeOutAssert
{
def
apply
(
signal
:
Bool
,
threshold
:
Int
,
message
:
String
)
:
Unit
=
{
def
apply
(
signal
:
Bool
,
message
:
String
,
threshold
:
Int
=
200000
)
:
Unit
=
{
val
counter
=
RegInit
(
0.
U
(
32.
W
))
when
(
signal
)
{
counter
:=
counter
+
1.
U
}.
otherwise
{
counter
:=
0.
U
}
assert
(
counter
<=
threshold
.
U
,
message
)
assert
(
counter
<=
threshold
.
U
,
s
"9527: $message"
)
}
}
\ No newline at end of file
}
src/main/scala/xiangshan/backend/issue/StatusArray.scala
浏览文件 @
5374af55
...
...
@@ -179,6 +179,7 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
val
realUpdateValid
=
updateValid
(
i
)
&&
!
io
.
redirect
.
valid
statusNext
.
valid
:=
!
flushedVec
(
i
)
&&
(
realUpdateValid
||
status
.
valid
)
XSError
(
updateValid
(
i
)
&&
status
.
valid
,
p
"should not update a valid entry $i\n"
)
TimeOutAssert
(
status
.
valid
,
s
"entry $i timeout\n"
,
40000
)
// scheduled: when the entry is scheduled for issue, mark it true.
// Set when (1) scheduled for issue; (2) enq blocked.
...
...
@@ -200,14 +201,14 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
if
(
params
.
checkWaitBit
)
{
val
blockNotReleased
=
isAfter
(
statusNext
.
sqIdx
,
io
.
stIssuePtr
)
val
storeAddrWaitforIsIssuing
=
VecInit
((
0
until
StorePipelineWidth
).
map
(
i
=>
{
io
.
memWaitUpdateReq
.
staIssue
(
i
).
valid
&&
io
.
memWaitUpdateReq
.
staIssue
(
i
).
valid
&&
io
.
memWaitUpdateReq
.
staIssue
(
i
).
bits
.
uop
.
robIdx
.
value
===
statusNext
.
waitForRobIdx
.
value
})).
asUInt
.
orR
&&
!
statusNext
.
waitForStoreData
&&
!
statusNext
.
strictWait
// is waiting for store addr ready
val
storeDataWaitforIsIssuing
=
VecInit
((
0
until
StorePipelineWidth
).
map
(
i
=>
{
io
.
memWaitUpdateReq
.
stdIssue
(
i
).
valid
&&
io
.
memWaitUpdateReq
.
stdIssue
(
i
).
valid
&&
io
.
memWaitUpdateReq
.
stdIssue
(
i
).
bits
.
uop
.
sqIdx
.
value
===
statusNext
.
waitForSqIdx
.
value
})).
asUInt
.
orR
&&
statusNext
.
waitForStoreData
statusNext
.
blocked
:=
Mux
(
updateValid
(
i
),
updateVal
(
i
).
blocked
,
status
.
blocked
)
&&
statusNext
.
blocked
:=
Mux
(
updateValid
(
i
),
updateVal
(
i
).
blocked
,
status
.
blocked
)
&&
!
storeAddrWaitforIsIssuing
&&
!
storeDataWaitforIsIssuing
&&
blockNotReleased
...
...
src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
浏览文件 @
5374af55
...
...
@@ -488,9 +488,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents {
when
(
s3_sc_fail
)
{
debug_sc_fail_addr
:=
s3_req
.
addr
debug_sc_fail_cnt
:=
1.
U
when
(
s3_sc_fail
===
100.
U
){
printf
(
"[WARN] L1DCache failed too many SCs in a row (0x%x), check if sth went wrong\n"
,
debug_sc_fail_addr
)
}
XSWarn
(
s3_sc_fail
===
100.
U
,
"L1DCache failed too many SCs in a row (0x%x), check if sth went wrong\n"
,
debug_sc_fail_addr
)
}
}
}
...
...
src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
浏览文件 @
5374af55
...
...
@@ -53,7 +53,7 @@ class MissReq(implicit p: Parameters) extends DCacheBundle {
// * cancel is slow to generate, it will not be used until the last moment
//
// cancel may come from the following sources:
// 1. miss req blocked by writeback queue:
// 1. miss req blocked by writeback queue:
// a writeback req of the same address is in progress
// 2. pmp check failed
val
cancel
=
Bool
()
// cancel is slow to generate, it will cancel missreq.valid
...
...
@@ -481,10 +481,13 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
val
tag
=
UInt
(
tagBits
.
W
)
// paddr
}))
})
// 128KBL1: FIXME: provide vaddr for l2
val
entries
=
Seq
.
fill
(
cfg
.
nMissEntries
)(
Module
(
new
MissEntry
(
edge
)))
for
((
entry
,
i
)
<-
entries
.
zipWithIndex
)
{
TimeOutAssert
(!
entry
.
io
.
primary_ready
,
s
"L1D MSHR $i timeout\n"
)
}
val
primary_ready_vec
=
entries
.
map
(
_
.
io
.
primary_ready
)
val
secondary_ready_vec
=
entries
.
map
(
_
.
io
.
secondary_ready
)
...
...
@@ -512,7 +515,7 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
if
(
name
.
nonEmpty
)
{
out
.
suggestName
(
s
"${name.get}_select"
)
}
out
.
valid
:=
Cat
(
in
.
map
(
_
.
valid
)).
orR
out
.
bits
:=
ParallelMux
(
in
.
map
(
_
.
valid
)
zip
in
.
map
(
_
.
bits
))
in
.
map
(
_
.
ready
:=
out
.
ready
)
in
.
map
(
_
.
ready
:=
out
.
ready
)
assert
(!
RegNext
(
out
.
valid
&&
PopCount
(
Cat
(
in
.
map
(
_
.
valid
)))
>
1.
U
))
}
...
...
@@ -521,15 +524,15 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
entries
.
zipWithIndex
.
foreach
{
case
(
e
,
i
)
=>
val
former_primary_ready
=
if
(
i
==
0
)
false
.
B
false
.
B
else
Cat
((
0
until
i
).
map
(
j
=>
entries
(
j
).
io
.
primary_ready
)).
orR
e
.
io
.
id
:=
i
.
U
e
.
io
.
req
.
valid
:=
io
.
req
.
valid
e
.
io
.
primary_valid
:=
io
.
req
.
valid
&&
!
merge
&&
!
reject
&&
e
.
io
.
primary_valid
:=
io
.
req
.
valid
&&
!
merge
&&
!
reject
&&
!
former_primary_ready
&&
e
.
io
.
primary_ready
e
.
io
.
req
.
bits
:=
io
.
req
.
bits
...
...
src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
浏览文件 @
5374af55
...
...
@@ -225,7 +225,7 @@ class L2TlbMissQueue(implicit p: Parameters) extends XSModule with HasPtwConst w
XSPerfAccumulate
(
"blocked_in"
,
io
.
in
.
valid
&&
!
io
.
in
.
ready
)
for
(
i
<-
0
until
MSHRSize
)
{
TimeOutAssert
(
state
(
i
)
=/=
state_idle
,
timeOutThreshold
,
s
"missqueue time out no out ${i}"
)
TimeOutAssert
(
state
(
i
)
=/=
state_idle
,
s
"missqueue time out no out ${i}"
)
}
val
perfEvents
=
Seq
(
...
...
src/main/scala/xiangshan/cache/mmu/PTW.scala
浏览文件 @
5374af55
...
...
@@ -324,8 +324,8 @@ class PTWImp(outer: PTW)(implicit p: Parameters) extends PtwModule(outer) with H
// time out assert
for
(
i
<-
0
until
MemReqWidth
)
{
TimeOutAssert
(
waiting_resp
(
i
),
timeOutThreshold
,
s
"ptw mem resp time out wait_resp${i}"
)
TimeOutAssert
(
flush_latch
(
i
),
timeOutThreshold
,
s
"ptw mem resp time out flush_latch${i}"
)
TimeOutAssert
(
waiting_resp
(
i
),
s
"ptw mem resp time out wait_resp${i}"
)
TimeOutAssert
(
flush_latch
(
i
),
s
"ptw mem resp time out flush_latch${i}"
)
}
...
...
src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
浏览文件 @
5374af55
...
...
@@ -191,7 +191,7 @@ class PtwFsm()(implicit p: Parameters) extends XSModule with HasPtwConst with Ha
XSPerfAccumulate
(
"mem_cycle"
,
BoolStopWatch
(
mem
.
req
.
fire
,
mem
.
resp
.
fire
(),
true
))
XSPerfAccumulate
(
"mem_blocked"
,
mem
.
req
.
valid
&&
!
mem
.
req
.
ready
)
TimeOutAssert
(
state
=/=
s_idle
,
timeOutThreshold
,
"page table walker time out"
)
TimeOutAssert
(
state
=/=
s_idle
,
"page table walker time out"
)
val
perfEvents
=
Seq
(
(
"fsm_count "
,
io
.
req
.
fire
()
),
...
...
src/main/scala/xiangshan/cache/mmu/Repeater.scala
浏览文件 @
5374af55
...
...
@@ -78,7 +78,7 @@ class PTWRepeater(Width: Int = 1)(implicit p: Parameters) extends XSModule with
XSDebug
(
req_in
.
valid
||
io
.
tlb
.
resp
.
valid
,
p
"tlb: ${tlb}\n"
)
XSDebug
(
io
.
ptw
.
req
(
0
).
valid
||
io
.
ptw
.
resp
.
valid
,
p
"ptw: ${ptw}\n"
)
assert
(!
RegNext
(
recv
&&
io
.
ptw
.
resp
.
valid
,
init
=
false
.
B
),
"re-receive ptw.resp"
)
TimeOutAssert
(
sent
&&
!
recv
,
timeOutThreshold
,
"Repeater doesn't recv resp in time"
)
TimeOutAssert
(
sent
&&
!
recv
,
"Repeater doesn't recv resp in time"
)
}
/* dtlb
...
...
@@ -316,7 +316,7 @@ class PTWFilter(Width: Int, Size: Int)(implicit p: Parameters) extends XSModule
}
for
(
i
<-
0
until
Size
)
{
TimeOutAssert
(
v
(
i
),
timeOutThreshold
,
s
"Filter ${i} doesn't recv resp in time"
)
TimeOutAssert
(
v
(
i
),
s
"Filter ${i} doesn't recv resp in time"
)
}
}
...
...
src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
浏览文件 @
5374af55
...
...
@@ -293,6 +293,7 @@ class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMiss
entry
.
io
.
req
.
valid
:=
io
.
req
(
i
).
valid
entry
.
io
.
req
.
bits
:=
io
.
req
(
i
).
bits
io
.
req
(
i
).
ready
:=
entry
.
io
.
req
.
ready
TimeOutAssert
(!
entry
.
io
.
req
.
ready
,
s
"L1I MSHR $i timeout\n"
)
// entry resp
meta_write_arb
.
io
.
in
(
i
)
<>
entry
.
io
.
meta_write
...
...
@@ -361,6 +362,3 @@ class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMiss
}
}
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