memory: add memory package

src/main/scala/gpu/GPU.scala

@@ -3,7 +3,7 @@ package gpu
 import chisel3._
 import chisel3.util._
 
-import noop.MemIO
+import memory.MemIO
 
 class PixelBundle extends Bundle {
   val a = UInt(8.W)

src/main/scala/memory/Bundle.scala

+package memory
+
+import chisel3._
+import chisel3.util._
+
+class MemAddrBundle extends Bundle {
+  val addr = Output(UInt(32.W))
+  val size = Output(UInt(3.W))
+}
+
+class MemDataBundle(val dataBits: Int) extends Bundle {
+  val data = Output(UInt(dataBits.W))
+}
+
+class MemMaskDataBundle(dataBits: Int) extends MemDataBundle(dataBits) {
+  val mask = Output(UInt((dataBits / 8).W))
+}
+
+class MemIO(val dataBits: Int = 32) extends Bundle {
+  val a = Valid(new MemAddrBundle)
+  val r = Flipped(Valid(new MemDataBundle(dataBits)))
+  val w = Valid(new MemMaskDataBundle(dataBits))
+}

src/main/scala/top/DistributedMem.scala → src/main/scala/memory/DistributedMem.scala

-package top
-
-import noop.MemIO
+package memory
 
 import chisel3._
 import chisel3.util._

src/main/scala/noop/Bundle.scala

@@ -44,22 +44,3 @@ class BranchIO extends Bundle {
   val isTaken = Output(Bool())
   val target = Output(UInt(32.W))
 }
-
-class MemAddrBundle extends Bundle {
-  val addr = Output(UInt(32.W))
-  val size = Output(UInt(3.W))
-}
-
-class MemDataBundle(val dataBits: Int) extends Bundle {
-  val data = Output(UInt(dataBits.W))
-}
-
-class MemMaskDataBundle(dataBits: Int) extends MemDataBundle(dataBits) {
-  val mask = Output(UInt((dataBits / 8).W))
-}
-
-class MemIO(val dataBits: Int = 32) extends Bundle {
-  val a = Valid(new MemAddrBundle)
-  val r = Flipped(Valid(new MemDataBundle(dataBits)))
-  val w = Valid(new MemMaskDataBundle(dataBits))
-}

src/main/scala/noop/EXU.scala

@@ -3,6 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 object LookupTree {
   private val useMuxTree = true
 

src/main/scala/noop/IFU.scala

@@ -3,6 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 trait HasResetVector {
   val resetVector = 0x80100000L
 }

src/main/scala/noop/NOOP.scala

@@ -3,6 +3,7 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
 import gpu.GPU
 
 trait NOOPConfig {

src/main/scala/noop/fu/LSU.scala

@@ -3,6 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 trait HasLSUOpType {
   val LsuOpTypeNum  = 10
 

src/test/scala/top/NOOPSim.scala

@@ -5,6 +5,8 @@ import noop._
 import chisel3._
 import chisel3.util._
 
+import memory.DistributedMem
+
 class NOOPSimTop(memInitFile: String = "") extends Module {
   val io = IO(new Bundle{
     val trap = Output(UInt((3 + 1 + 4 + 32 + 32 + 2).W))

src/test/scala/top/SimMMIO.scala

 package top
 
-import noop.MemIO
-
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 class SimMMIO extends Module {
   val io = IO(new Bundle {
     val rw = Flipped(new MemIO)