From 52fcd981d213af1382ed1727b0f3fac4c9281f90 Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Sat, 16 Feb 2019 11:14:13 +0800
Subject: [PATCH] memory: add memory package

---
 src/main/scala/gpu/GPU.scala                  |  2 +-
 src/main/scala/memory/Bundle.scala            | 23 +++++++++++++++++++
 .../{top => memory}/DistributedMem.scala      |  4 +---
 src/main/scala/noop/Bundle.scala              | 19 ---------------
 src/main/scala/noop/EXU.scala                 |  2 ++
 src/main/scala/noop/IFU.scala                 |  2 ++
 src/main/scala/noop/NOOP.scala                |  1 +
 src/main/scala/noop/fu/LSU.scala              |  2 ++
 src/test/scala/top/NOOPSim.scala              |  2 ++
 src/test/scala/top/SimMMIO.scala              |  4 ++--
 10 files changed, 36 insertions(+), 25 deletions(-)
 create mode 100644 src/main/scala/memory/Bundle.scala
 rename src/main/scala/{top => memory}/DistributedMem.scala (98%)

diff --git a/src/main/scala/gpu/GPU.scala b/src/main/scala/gpu/GPU.scala
index e2cf36a47..3eabdeaaa 100644
--- a/src/main/scala/gpu/GPU.scala
+++ b/src/main/scala/gpu/GPU.scala
@@ -3,7 +3,7 @@ package gpu
 import chisel3._
 import chisel3.util._
 
-import noop.MemIO
+import memory.MemIO
 
 class PixelBundle extends Bundle {
   val a = UInt(8.W)
diff --git a/src/main/scala/memory/Bundle.scala b/src/main/scala/memory/Bundle.scala
new file mode 100644
index 000000000..bdd44a776
--- /dev/null
+++ b/src/main/scala/memory/Bundle.scala
@@ -0,0 +1,23 @@
+package memory
+
+import chisel3._
+import chisel3.util._
+
+class MemAddrBundle extends Bundle {
+  val addr = Output(UInt(32.W))
+  val size = Output(UInt(3.W))
+}
+
+class MemDataBundle(val dataBits: Int) extends Bundle {
+  val data = Output(UInt(dataBits.W))
+}
+
+class MemMaskDataBundle(dataBits: Int) extends MemDataBundle(dataBits) {
+  val mask = Output(UInt((dataBits / 8).W))
+}
+
+class MemIO(val dataBits: Int = 32) extends Bundle {
+  val a = Valid(new MemAddrBundle)
+  val r = Flipped(Valid(new MemDataBundle(dataBits)))
+  val w = Valid(new MemMaskDataBundle(dataBits))
+}
diff --git a/src/main/scala/top/DistributedMem.scala b/src/main/scala/memory/DistributedMem.scala
similarity index 98%
rename from src/main/scala/top/DistributedMem.scala
rename to src/main/scala/memory/DistributedMem.scala
index 983e39795..1ca22c9a7 100644
--- a/src/main/scala/top/DistributedMem.scala
+++ b/src/main/scala/memory/DistributedMem.scala
@@ -1,6 +1,4 @@
-package top
-
-import noop.MemIO
+package memory
 
 import chisel3._
 import chisel3.util._
diff --git a/src/main/scala/noop/Bundle.scala b/src/main/scala/noop/Bundle.scala
index 41d7e705d..0bd2296a8 100644
--- a/src/main/scala/noop/Bundle.scala
+++ b/src/main/scala/noop/Bundle.scala
@@ -44,22 +44,3 @@ class BranchIO extends Bundle {
   val isTaken = Output(Bool())
   val target = Output(UInt(32.W))
 }
-
-class MemAddrBundle extends Bundle {
-  val addr = Output(UInt(32.W))
-  val size = Output(UInt(3.W))
-}
-
-class MemDataBundle(val dataBits: Int) extends Bundle {
-  val data = Output(UInt(dataBits.W))
-}
-
-class MemMaskDataBundle(dataBits: Int) extends MemDataBundle(dataBits) {
-  val mask = Output(UInt((dataBits / 8).W))
-}
-
-class MemIO(val dataBits: Int = 32) extends Bundle {
-  val a = Valid(new MemAddrBundle)
-  val r = Flipped(Valid(new MemDataBundle(dataBits)))
-  val w = Valid(new MemMaskDataBundle(dataBits))
-}
diff --git a/src/main/scala/noop/EXU.scala b/src/main/scala/noop/EXU.scala
index af9e31e19..40c37b044 100644
--- a/src/main/scala/noop/EXU.scala
+++ b/src/main/scala/noop/EXU.scala
@@ -3,6 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 object LookupTree {
   private val useMuxTree = true
 
diff --git a/src/main/scala/noop/IFU.scala b/src/main/scala/noop/IFU.scala
index 35a44a190..0b2340dd2 100644
--- a/src/main/scala/noop/IFU.scala
+++ b/src/main/scala/noop/IFU.scala
@@ -3,6 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 trait HasResetVector {
   val resetVector = 0x80100000L
 }
diff --git a/src/main/scala/noop/NOOP.scala b/src/main/scala/noop/NOOP.scala
index eaefb2033..0869b3839 100644
--- a/src/main/scala/noop/NOOP.scala
+++ b/src/main/scala/noop/NOOP.scala
@@ -3,6 +3,7 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
 import gpu.GPU
 
 trait NOOPConfig {
diff --git a/src/main/scala/noop/fu/LSU.scala b/src/main/scala/noop/fu/LSU.scala
index 3de7e0efc..096be6eaa 100644
--- a/src/main/scala/noop/fu/LSU.scala
+++ b/src/main/scala/noop/fu/LSU.scala
@@ -3,6 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 trait HasLSUOpType {
   val LsuOpTypeNum  = 10
 
diff --git a/src/test/scala/top/NOOPSim.scala b/src/test/scala/top/NOOPSim.scala
index 949b453d7..35b8e3875 100644
--- a/src/test/scala/top/NOOPSim.scala
+++ b/src/test/scala/top/NOOPSim.scala
@@ -5,6 +5,8 @@ import noop._
 import chisel3._
 import chisel3.util._
 
+import memory.DistributedMem
+
 class NOOPSimTop(memInitFile: String = "") extends Module {
   val io = IO(new Bundle{
     val trap = Output(UInt((3 + 1 + 4 + 32 + 32 + 2).W))
diff --git a/src/test/scala/top/SimMMIO.scala b/src/test/scala/top/SimMMIO.scala
index 7d8e168af..aa040b1d1 100644
--- a/src/test/scala/top/SimMMIO.scala
+++ b/src/test/scala/top/SimMMIO.scala
@@ -1,10 +1,10 @@
 package top
 
-import noop.MemIO
-
 import chisel3._
 import chisel3.util._
 
+import memory.MemIO
+
 class SimMMIO extends Module {
   val io = IO(new Bundle {
     val rw = Flipped(new MemIO)
-- 
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