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体验新版 GitCode,发现更多精彩内容 >>
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52bd42c2
编写于
8月 17, 2020
作者:
Y
Yinan Xu
浏览文件
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电子邮件补丁
差异文件
lsroq: optimize lsroqViolation logic
上级
5c18a2d3
变更
1
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并排
Showing
1 changed file
with
21 addition
and
20 deletion
+21
-20
src/main/scala/xiangshan/mem/Lsroq.scala
src/main/scala/xiangshan/mem/Lsroq.scala
+21
-20
未找到文件。
src/main/scala/xiangshan/mem/Lsroq.scala
浏览文件 @
52bd42c2
...
@@ -434,8 +434,9 @@ class Lsroq extends XSModule {
...
@@ -434,8 +434,9 @@ class Lsroq extends XSModule {
def
getFirstOne
(
mask
:
Vec
[
Bool
],
start
:
UInt
)
=
{
def
getFirstOne
(
mask
:
Vec
[
Bool
],
start
:
UInt
)
=
{
val
length
=
mask
.
length
val
length
=
mask
.
length
val
lowMask
=
(
1.
U
((
length
+
1
).
W
)
<<
start
).
asUInt
()
-
1.
U
val
lowMask
=
(
1.
U
((
length
+
1
).
W
)
<<
start
).
asUInt
()
-
1.
U
val
highBits
=
(
0
until
length
).
map
(
i
=>
mask
(
i
)
&
lowMask
(
i
))
val
highBits
=
(
0
until
length
).
map
(
i
=>
mask
(
i
)
&
~
lowMask
(
i
))
Mux
(
Cat
(
highBits
).
orR
(),
PriorityEncoder
(
highBits
),
PriorityEncoder
(
mask
))
val
highBitsUint
=
Cat
(
highBits
.
reverse
)
PriorityEncoder
(
Mux
(
highBitsUint
.
orR
(),
highBitsUint
,
mask
.
asUInt
))
}
}
def
getOldestInTwo
(
valid
:
Seq
[
Bool
],
uop
:
Seq
[
MicroOp
])
=
{
def
getOldestInTwo
(
valid
:
Seq
[
Bool
],
uop
:
Seq
[
MicroOp
])
=
{
...
@@ -458,33 +459,33 @@ class Lsroq extends XSModule {
...
@@ -458,33 +459,33 @@ class Lsroq extends XSModule {
})
})
}
}
def
rangeMask
(
start
:
UInt
,
end
:
UInt
)
:
UInt
=
{
val
startMask
=
(
1.
U
((
LsroqSize
+
1
).
W
)
<<
start
(
InnerLsroqIdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
endMask
=
(
1.
U
((
LsroqSize
+
1
).
W
)
<<
end
(
InnerLsroqIdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
xorMask
=
startMask
(
LsroqSize
-
1
,
0
)
^
endMask
(
LsroqSize
-
1
,
0
)
Mux
(
start
(
InnerLsroqIdxWidth
)
===
end
(
InnerLsroqIdxWidth
),
xorMask
,
~
xorMask
)
}
// store backward query and rollback
// store backward query and rollback
// val needCheck = Seq.fill(8)(WireInit(true.B))
// val needCheck = Seq.fill(8)(WireInit(true.B))
(
0
until
StorePipelineWidth
).
foreach
(
i
=>
{
(
0
until
StorePipelineWidth
).
foreach
(
i
=>
{
rollback
(
i
)
:=
DontCare
rollback
(
i
)
:=
DontCare
when
(
io
.
storeIn
(
i
).
valid
)
{
when
(
io
.
storeIn
(
i
).
valid
)
{
val
needCheck
=
Seq
.
fill
(
LsroqSize
+
1
)(
Seq
.
fill
(
8
)(
WireInit
(
true
.
B
)))
// TODO: refactor
val
startIndex
=
io
.
storeIn
(
i
).
bits
.
uop
.
lsroqIdx
(
InnerLsroqIdxWidth
-
1
,
0
)
val
toEnqPtrMask
=
rangeMask
(
io
.
storeIn
(
i
).
bits
.
uop
.
lsroqIdx
,
ringBufferHeadExtended
)
val
lsroqViolationVec
=
VecInit
((
0
until
LsroqSize
).
map
(
j
=>
{
val
lsroqViolationVec
=
VecInit
((
0
until
LsroqSize
).
map
(
j
=>
{
val
ptr
=
io
.
storeIn
(
i
).
bits
.
uop
.
lsroqIdx
+
j
.
U
val
addrMatch
=
allocated
(
j
)
&&
val
reachHead
=
(
ptr
+
1.
U
)
===
ringBufferHeadExtended
io
.
storeIn
(
i
).
bits
.
paddr
(
PAddrBits
-
1
,
3
)
===
data
(
j
).
paddr
(
PAddrBits
-
1
,
3
)
val
addrMatch
=
allocated
(
ptr
)
&&
val
entryNeedCheck
=
toEnqPtrMask
(
j
)
&&
addrMatch
&&
!
store
(
j
)
&&
valid
(
j
)
io
.
storeIn
(
i
).
bits
.
paddr
(
PAddrBits
-
1
,
3
)
===
data
(
ptr
).
paddr
(
PAddrBits
-
1
,
3
)
// TODO: update refilled data
val
mask
=
data
(
ptr
).
mask
val
violationVec
=
(
0
until
8
).
map
(
k
=>
data
(
j
).
mask
(
k
)
&&
io
.
storeIn
(
i
).
bits
.
mask
(
k
))
val
s
=
store
(
ptr
)
Cat
(
violationVec
).
orR
()
&&
entryNeedCheck
val
w
=
writebacked
(
ptr
)
val
v
=
valid
(
ptr
)
val
violationVec
=
(
0
until
8
)
map
(
k
=>
{
needCheck
(
j
+
1
)(
k
)
:=
needCheck
(
j
)(
k
)
&&
!(
addrMatch
&&
s
&&
mask
(
k
))
&&
!
reachHead
needCheck
(
j
)(
k
)
&&
addrMatch
&&
mask
(
k
)
&&
io
.
storeIn
(
i
).
bits
.
mask
(
k
)
&&
!
s
&&
v
// TODO: update refilled data
})
Cat
(
violationVec
).
orR
()
}))
}))
val
lsroqViolation
=
lsroqViolationVec
.
asUInt
().
orR
()
val
lsroqViolation
=
lsroqViolationVec
.
asUInt
().
orR
()
val
lsroqViolationIndex
=
io
.
storeIn
(
i
).
bits
.
uop
.
lsroqIdx
+
PriorityEncoder
(
lsroqViolationVec
)
val
lsroqViolationIndex
=
getFirstOne
(
lsroqViolationVec
,
startIndex
)
val
lsroqViolationUop
=
uop
(
lsroqViolationIndex
)
val
lsroqViolationUop
=
uop
(
lsroqViolationIndex
)
XSDebug
(
lsroqViolation
,
p
"${Binary(Cat(lsroqViolationVec))}, $
lsroqViolationIndex
"
)
XSDebug
(
lsroqViolation
,
p
"${Binary(Cat(lsroqViolationVec))}, $
startIndex, $lsroqViolationIndex\n
"
)
// when l/s writeback to roq together, check if rollback is needed
// when l/s writeback to roq together, check if rollback is needed
val
wbViolationVec
=
VecInit
((
0
until
LoadPipelineWidth
).
map
(
j
=>
{
val
wbViolationVec
=
VecInit
((
0
until
LoadPipelineWidth
).
map
(
j
=>
{
...
@@ -495,7 +496,7 @@ class Lsroq extends XSModule {
...
@@ -495,7 +496,7 @@ class Lsroq extends XSModule {
}))
}))
val
wbViolation
=
wbViolationVec
.
asUInt
().
orR
()
val
wbViolation
=
wbViolationVec
.
asUInt
().
orR
()
val
wbViolationUop
=
getOldestInTwo
(
wbViolationVec
,
io
.
loadIn
.
map
(
_
.
bits
.
uop
))
val
wbViolationUop
=
getOldestInTwo
(
wbViolationVec
,
io
.
loadIn
.
map
(
_
.
bits
.
uop
))
XSDebug
(
wbViolation
,
p
"${Binary(Cat(wbViolationVec))}, $wbViolationUop"
)
XSDebug
(
wbViolation
,
p
"${Binary(Cat(wbViolationVec))}, $wbViolationUop
\n
"
)
// check if rollback is needed for load in l4
// check if rollback is needed for load in l4
val
l4ViolationVec
=
VecInit
((
0
until
LoadPipelineWidth
).
map
(
j
=>
{
val
l4ViolationVec
=
VecInit
((
0
until
LoadPipelineWidth
).
map
(
j
=>
{
...
...
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